Prof. D. Zhou UT Dallas Analog Circuits Design Automation 1.

Slides:



Advertisements
Similar presentations
A Fast Estimation of SRAM Failure Rate Using Probability Collectives Fang Gong Electrical Engineering Department, UCLA Collaborators:
Advertisements

Joint Design-Time and Post-Silicon Optimization for Analog Circuits: A Case Study Using High-Speed Transmitter Yiyu Shi, Wei Yao, Lei He, and Sudhakar.
Melih Papila, Piezoresistive microphone design Pareto optimization: Tradeoff between sensitivity and noise floor Melih PapilaMark Sheplak.
Transmission Line Network For Multi-GHz Clock Distribution Hongyu Chen and Chung-Kuan Cheng Department of Computer Science and Engineering, University.
NxN pixel demonstrator. Time to Digital Converter (2) Tapped delay line –128 cells, 100ps Two hit registers –One per both leading and trailing edge 7.
Prof. D. Zhou UT Dallas Analog Circuits Design Automation 1.
Specification Test Minimization for Given Defect Level Suraj Sindia Intel Corporation, Hillsboro, OR 97124, USA Vishwani D. Agrawal.
Worst Case Analysis Using Analog Workbench by Andrew G. Bell ITT Industries.
Stochastic Analog Circuit Behavior Modeling by Point Estimation Method
Approaches to Data Acquisition The LCA depends upon data acquisition Qualitative vs. Quantitative –While some quantitative analysis is appropriate, inappropriate.
GoldSim 2006 User Conference Slide 1 Vancouver, B.C. The Submodel Element.
Evolutionary Synthesis of MEMS Design Ningning Zhou, Alice Agogino, Bo Zhu, Kris Pister*, Raffi Kamalian Department of Mechanical Engineering, *Department.
Fall 06, Sep 19, 21 ELEC / Lecture 6 1 ELEC / (Fall 2005) Special Topics in Electrical Engineering Low-Power Design of Electronic.
MAE 552 – Heuristic Optimization Lecture 6 February 6, 2002.
Analysis on Performance Controllability under Process Variability: A Step Towards Grid-Based Analog Circuit Optimizers Seobin Jung Mixed-Signal IC and.
Department of Electrical and Computer Engineering System-Level Simulation for Continuous-Time Delta-Sigma Modulator in MATLAB SIMULINK MATTHEW WEBB, HUA.
1 Enhancing Performance of Iterative Heuristics for VLSI Netlist Partitioning Dr. Sadiq M. Sait Dr. Aiman El-Maleh Mr. Raslan Al Abaji. Computer Engineering.
PH4705/ET4305: Instrumentation Amp Our sensor will be connected to some kind of measurement system either directly, diag. 1, or as a bridge circuit diag.
Prof. D. Zhou UT Dallas Analog Circuits Design Automation 1.
An amplifier with a transistor that conducts during the entire 360º of the input signal cycle. Optimum class A operation is obtained by designing an amplifier.
Prof. D. Zhou UT Dallas Analog Circuits Design Automation 1.
Prof. D. Zhou UT Dallas Analog Circuits Design Automation 1.
Black Box Electronics An Introduction to Applied Electronics for Physicists 2. Analog Electronics: BJTs to opamps University of Toronto Quantum Optics.
A Wideband CMOS Current-Mode Operational Amplifier and Its Use for Band-Pass Filter Realization Mustafa Altun *, Hakan Kuntman * * Istanbul Technical University,
Steve Grout CAD Consultant April 26, 2004 Missing Analog Tools – A Proposal Analog/Mixed Signal SoC Methodologies.
Optimization based Method for Circuit Performance Robustness Analysis and Design Automation Liuxi Qian The University of Texas at Dallas 1.
Ranga Rodrigo April 6, 2014 Most of the sides are from the Matlab tutorial. 1.
Graduate Category: Engineering and Technology Degree Level: Ph.D. Abstract ID# 122 On-Chip Spectral Analysis for Built-In Testing and Digital Calibration.
CMOS Op-Amp Power Optimization in All Regions of Inversion Using Geometric Programming Pablo Aguirre and Fernando Silveira IIE – FING Universidad de la.
Final Project in RFCS in the MINT Program of the UPC by Sven Günther
18/10/20151 Calibration of Input-Matching and its Center Frequency for an Inductively Degenerated Low Noise Amplifier Laboratory of Electronics and Information.
Chapter 4 Stochastic Modeling Prof. Lei He Electrical Engineering Department University of California, Los Angeles URL: eda.ee.ucla.edu
1 5. Application Examples 5.1. Programmable compensation for analog circuits (Optimal tuning) 5.2. Programmable delays in high-speed digital circuits (Clock.
W3,4: Operational Amplifier Design Insoo Kim, Jaehyun Lim, Kyungtae Kang Mixed Signal CHIP Design Lab. Department of Computer Science & Engineering The.
class B, AB and D rf power amplifiers in 0,40 um cmos teChnology
ECE 342 – Jose Schutt-Aine 1 ECE 342 Solid-State Devices & Circuits 16. Active Loads Jose E. Schutt-Aine Electrical & Computer Engineering University of.
POWER AMPLIFIER Class B Class AB Class C.
QuickYield: An Efficient Global-Search Based Parametric Yield Estimation with Performance Constraints Fang Gong 1, Hao Yu 2, Yiyu Shi 1, Daesoo Kim 1,
Rakshith Venkatesh 14/27/2009. What is an RF Low Noise Amplifier? The low-noise amplifier (LNA) is a special type of amplifier used in the receiver side.
1 5. Application Examples 5.1. Programmable compensation for analog circuits (Optimal tuning) 5.2. Programmable delays in high-speed digital circuits (Clock.
Tae- Hyoung Kim, Hanyong Eom, John Keane Presented by Mandeep Singh
Outline Abstract Introduction Bluetooth receiver architecture
Simulated Annealing To minimize the wire length. Combinatorial Optimization The Process of searching the solution space for optimum possible solutions.
HW5 and Final Project Yield Estimation and Optimization for 6-T SRAM Cell Fang Gong
M. R. Gouvea BR Session 1 – Block 1 – Transformers – Paper #36 Barcelona May RISK CRITERIA TO APPLY AND MANAGE DISTRIBUTION TRANSFORMERS M.
CMOS 2-Stage OP AMP 설계 DARK HORSE 이 용 원 홍 길 선
Submitted by- RAMSHANKAR KUMAR S7,ECE, DOE,CUSAT Division of Electronics Engineering, SOE,CUSAT1.
Copyright 2012, AgrawalLecture 12: Alternate Test1 VLSI Testing Lecture 12: Alternate Test Dr. Vishwani D. Agrawal James J. Danaher Professor of Electrical.
Warehouse Lending Optimization Paul Parker (2016).
Quiz: Determining a SAR ADC’s Linear Range when using Operational Amplifiers TIPL 4101 TI Precision Labs – ADCs Created by Art Kay.
Communication 40 GHz Anurag Nigam.
B.Sc. Thesis by Çağrı Gürleyük
CSE598A Analog Mixed Signal CMOS Chip Design
Fang Gong HW5 and Final Project Yield Estimation and Optimization for 6-T SRAM Cell Fang Gong
Particle Swarm Optimization
Amplifier Designer Stealth Release.
ELEC 7770: Advanced VLSI Design Spring Analog and RF Test Strategies
By Rohit Ray ESE 251 Simulated Annealing.
Basic Amplifiers and Differential Amplifier
EE201C Modeling of VLSI Circuits and Systems Final Project
VLSI Testing Lecture 12: Alternate Test
CMOS Technology Flow varies with process types & company
EE201C Modeling of VLSI Circuits and Systems Final Project
MCP Electronics Time resolution, costs
Design for Simple Spiking Neuron Model
CMOS Technology Flow varies with process types & company
Low Power Digital Design
Rare and Forbidden Decays in the Standard Model
Analog Senior Projects 2019
Stochastic Methods.
Presentation transcript:

Prof. D. Zhou UT Dallas Analog Circuits Design Automation 1

Design Optimization  Analog circuit design automation  For a design  Determine the specs  Choose the intended manufacture process  Choose the circuit topology  Determine the variables and their “ranges”  Transistor size, input and supply voltage, noise and etc.  Choose the simulation tool  SPICE, mixed signal and etc.  Construct the objective functions and constraints  Choose an efficient optimization method Analog Circuits Design Automation 2

Z.Yan, P.Mak, M.Law, R.P.Martins, "A mm^2 144µW Three-Stage Amplifier Capable of Driving 1-to-15 nF Capacitive Load With> 0.95-MHz GBW,"IEEE Journal of Solid-State Circuits, vol.48, no.2, pp.527,540, Feb

Manual Design TT,27°CFF,-40°CSS,125°Cσ / Mean GBW (MHz)≥ ≤ 25.8% PM (Degree)≥ ≤ 3.7% GM (dB)≥ ≤ 6.95% SR+(V/μs)≥ ≤ 31.6% SR- (V/μs)≥ ≤ 39.7% 1% Ts+(μs)≤ ≤ 25.5% 1% Ts- (μs)≤ ≤ 42.7% Min I Q (µA)≤ ≤ 2.2%  Performance Concerned: minimize current consumption  Parameter Space: device dimensions  Constraints: design specifications

 Two features make it outperform other methods “Region hit” issue vs. “Point hit” issue Guided search vs. random and independent search MC method used to find the global optimum MGO method used to find the global optimum None of 200 Monte Carlo sample points exactly hits the global optimum. Once a start point hits the region containing the global optimum, the global optimum can be found easily by a local optimization search. global optimum local optimum Sample points 5 global optimum local optimum Start point Region of attraction The probability for hitting a region is much larger than hitting a point!

6 Eason’s function Rastrigin’s function Six-hump camel back’s function Genetic, simulated annealing and particle swarm methods are using MATLAB build-in functions. The results are based on an average of 10 trials for each method. *Data source: Marcin Molga and Czeslaw Smutnicki, “Test functions for optimization needs,” in 2005.