SCI Communication Proudly Presented By: Adam Cardi & Aaron Enes

The outline of the presentation. Serial vs. Parallel Communication Synchronous vs. Asynchronous Serial Communication Baud and Bit Rates Asynchronous Serial Communication  Emphasis on HC11 implementation Explicit Outline of Data Transmission Process

Motivation. Suppose two devices need to communicate with one another…how can this be done? (a) Telephone (b) Smoke signals (c) Pony Express (d) Serial Communication

There are two major communication methods. Serial  One bit at a time on one data line  Slower than parallel transmission  Inexpensive  Example: modem, USB Parallel  N bits at a time over N data lines  Synchronization among all N bits  Faster than serial transmission  More expensive  Example: printer connections

Serial Parallel Transmitter Receiver 2 nd word 1 st word Transmitter Receiver 2 nd word 1 st word Hmm…how do I know where to start?

There are two breeds of serial communication. Synchronous  Additional clock signal to keep sync.  Bit transfer rate determined by the clock signal  Continuously transmitting characters to remain in sync. Asynchronous  No clock signal, intermittent data transfer  Uses fixed-size packets to keep sync.  Bit transfer rate preset by programmer  Transmission data contains information to synchronize receiver when receiving data

More on data transfer rates. Baud rate: net number of bits per second that can be transmitted, including overhead (start/stop/parity bits). Bit rate: number of data bits per second that can be transmitted.

Asynchronous Communication Most common form of serial communication Data is carried in fixed-size ‘packets’  Usually 8 data bits for word length  Bits are followed by a parity bit (optional) to verify signal integrity  Packet is surrounded by a start bit and stop bits (both zeros)

Asynchronous communication: anatomy of total data package Start BitData Bit 0Data Bit 1 Data Bit 2Data Bit 3Data Bit 4Data Bit 5Data Bit 6Data Bit 7 Parity BitStop Bit x52 start stop parity Bitstream was high before start bit

Start BitData Bit 0Data Bit 1 Data Bit 2Data Bit 3Data Bit 4Data Bit 5Data Bit 6Data Bit 7 Parity BitStop Bit x52 start stop parity If the Baud rate was set at 9600, then bitrate is 8/12*9600 = 6400 bps.

So what about that parity bit? Used to help verify signal integrity Even parity  Parity bit set or cleared such that the sum of all high bits (including the parity bit itself) is even Odd parity  Parity bit set or cleared such that the sum of all high bits (including the parity bit itself) is odd

More about parity. The type of parity is known a priori (determined by programmer) Parity bit calculated and set by software before transmission e.g. the HC11 knows nothing about parity Not used very often…better ways to check for errors…

An example of even parity. Start BitData Bit 0Data Bit 1 Data Bit 2Data Bit 3Data Bit 4Data Bit 5Data Bit 6Data Bit 7 Parity BitStop Bit x52 start stop parity ??????

Start bit—Ideal Case Receiver Idle

HC11’s got your back. Length (Time) of one serial bit Data receiving aborted!!!

Noise in action. Noise causes start bit to be detected too soon RT1, RT5 and RT7 are 0, so start will be accepted (majority rules) RT3 is 1, so noise flag will be set Period determine by baud rate Period determine by clock frequency (fixed)

The details of asynchronous serial data transmission on the 68HC11. 4 control and status registers:  BAUD – Sets the bit rate for the SCI system  SCCR1 – Sets control bits for the 9-bit character format and the receiver wake up feature  SCCR2 – Main control register for the SCI sub- system  SCSR – Status register for the SCI system 1 data register:  SCDR – Main data register for the SCI system Port D, pins 0 and 1 contain SCI Input/Output

SCDR Register SCI data register  Two separate registers, same address  Use it to Read the Received data  Use it to Write the Transmit data  R7 - R0 – Read bits  T7 - T0 – Write bits

SCCR1 Register Contains control bits to set Word length and Wakeup feature  M – SCI character length bit (to send either 8 or 9 bits)  R8, T8 – Receive and Transmit data bit 8 (for Parity)  WAKE – Wakeup method select bit  Bits 0:2 & 5 are not used (always 0) Parity bit can go here (optional)

SCCR2 Register Main control register for SCI sub-system  TIE – Transmit interrupt enable bit  TCIE – Transmit complete interrupt enable bit  RIE – Receive interrupt enable bit (Receive Data Register Full)  ILIE – Idle-line interrupt enable bit  TE – Transmit enable bit  RE – Receive enable bit  RWU – Receiver wakeup bit  SBK – Send break bit

SCSR Register SCI status register. Used for system interrupt.  TDRE – Transmit data register empty bit  TC – Transmit complete bit  RDRF – Receive data register full bit  IDLE – Idle-line detect bit  OR – Overrun error bit  NF – Noise flag  FE – Framing Error bit  Bit 0 is not used (always 0) Should be “0s” after data is received Will be “1” after data is received

The BAUD register BAUD register  TCLR – Clear baud rate timing chain bit  SCP[2:0]– Baud rate pre-scale select bits  RCKB –Baud rate clock test bit  SCR[2:0]– SCI baud rate select bits Address:$102B Bit Bit 0 Read: 00 Write: TCLRRCKB Reset:00000UUU U = Unaffected SCR1SCR0SCP00SCP1SCR2

Set Baud rate of transmitter  Must match Receiver Set M bit of SCCR1 for 8 or 9 bit data  Must match Receiver Set TE bit of SCCR2 high to enable transmitter Set Baud rate of receiver  Must match Transmitter Set M bit of SCCR1 for 8 or 9 bit data  Must match Transmitter Set RE bit of SCCR2 high to enable receiver How to Send and Receive Data Transmitter Receiver

Activate WAKE condition in SCCR1 register Load data character into SCDR When TDRE bit of SCSR register goes high, the SCDR register is clear and another character can be loaded Set WAKE bit on SCCR1 RDRF bit of SCSR set when all data has entered RDR Read data from RDR and Store Check flags (NF, FR, OR) for possible error protocols How to Send and Receive Data Transmitter Receiver

When TC bit of SCSR register goes high, transmit buffer clear Transmitter resumes Idle by sending stream of “1s” Receiver returns to wake/sleep mode previously set How to Send and Receive Data Transmitter Receiver

This program can be used to send data. * * Test program for transmitting for serial data. User * specifies 8-bit data. See below. * MAIN EQU $1040 *Assemble code here starting at $1040 PORTC EQU $1003 *Equate PORTC to $1003 DDRC EQU $1007 *Equate data direction register DDRC SCCR2 EQU $102D *Equate SCI control register 2 BAUD EQU $102B *Equate BAUD register SCSR EQU $102E *Equate SCI status register SCDR EQU $102F *Equate SCI data register *===========================PROGRAM========================================== ORG MAIN LDAA #$33 *Select 1200 baud. Refer to Pink book P9-7 STAA BAUD LDAA #$08 *Enable TX and RX STAA SCCR2 LOOP LDAA #$05 *Put data into TXD for transmission. User *specify data here! STAA SCDR *Put transmit data into SCI data register CHECK LDAA SCSR *Check to see if data has been transferred ANDA #$C0 CMPA #$C0 BNE CHECK BRA LOOP *Do it again

This program can be used to receive data. * * Test program for serial receive using MING RF Rx module. MCU waits for data * and then outputs received data to PORT C. Connect LEDs to PORT C to see the * 8-bit data that has been received. * MAIN EQU $1040 *Assemble code here starting at $1040 PORTC EQU $1003 *Equate PORTC to $1003 DDRC EQU $1007 *Equate data direction register DDRC SCCR2 EQU $102D *Equate SCI control register 2 BAUD EQU $102B *Equate BAUD register SCSR EQU $102E *Equate SCI status register SCDR EQU $102F *Equate SCI data register *===========================PROGRAM========================================== ORG MAIN LDAA #$FF *Load ACCA with $FF to config PORTC as input STAA DDRC LDAA #$33 *Select 1200 baud. Refer to Pink book P9-7 STAA BAUD LDAA #$04 *Enable RX STAA SCCR2 CHECK LDAA SCSR *Check to see if data has been received ANDA #$20 CMPA #$20 BNE CHECK *Branch back up to check if not received LDAA SCDR STAA PORTC *Send data to PORT C. Use LEDs on PORT C *to display received data. BRA CHECK *Repeat process *============================================================================