Status of FTK Paola Giannetti, INFN Pisa, for the FTK Group ATLAS Italia, Fabruary 2, 2010 Status & Evolution of FTK (impact on Italian groups) Schedule for the procedure: TDAQ first, USG after The collaboration – Hardware sharing FTK Schedule & Global Costs Milestones

Status & Evolution 2  3 x10 34 : 90% DONE see Draft Techinical Proposal performance studies: a good step in the TP– we can still improve - Again: New architecture  After approval split into multiple activities build the system for 3 x10 34 (2016?) ITALY 2 jobs:  Standard: AMboard (Pisa), Pixel clustering mezzanine (Frascati) – 2013?  Challenging: TSP and new AMchip → R&D – ready ? (Pisa-Frascati-Fermilab + someone else?) vertical (start 2012)→ protoFTK studies → insertion new prototypes → before (2015?) (Pisa-Frascati-Pavia-Bologna)

FTK Document Status & Plans =========================== * The document currently being written on FTK system will be called a Technical Proposal (TP) * A final draft of the TP will be available 15 February 2010 * A draft version of the document will be discussed with Italian referees from INFN in the course of February * Chris & David will identify people from TDAQ who would be prepared to review the document in detail. This review could begin informally before the document is finalized in order to gain time. o TDAQ review set up Nikos Konstantinidis, Nick Ellis, Aleandro Nisati, John Baines & Jos Vermeulen * Once this review is completed, the revised document would go to TDAQ for final comment * It is currently anticipated to submit the document to the Upgrade Steering Group (USG) by the middle of March * If the document is approved by the USG and we are encouraged to proceed to a TDR, it is estimated (subject to the scope of the TDR and the machine schedule) that a TDR would be produced 24 months after the approval by the USG of the TP. Schedule proposed by TDAQ to Upgrade Steering Group

Who signs the TP today University of Chicago USA M. Bogdan,A.Boveia, F. Canelli, M. Dunford, J.F. Genat, A. Kapliy, Y.K. Kim, C.Melachrinos, M.Shochet, F. Tang, J. Tuggle Laboratori Nazionali di Frascati A. Annovi, M. Beretta, G. Volpi Harward University M.Franklin, C. Mills, M. Morii University of Illinois USA M. Kasten, A. McCarn, M.S. Neubauer Dipartimento di Fisica e Istituto Nazionale Fisica Nucleare Pisa E. Bossini, F. Crescioli, M. Dell’Orso, P. Giannetti, M. Piendibene, C. Roda Argonne National Lab USA G. Drake, J. Proudfoot, J. Zhang Waseda University Japan Naoki Kimura, K. Yorita → → → → → → → Fermilab National Lab USA J. Hoff, T. Liu, B. Penning, M. Verzocchi, J.Y. Wu Dipartimento di Fisica e Istituto Nazionale Fisica Nucleare Pavia A. Negri, V. Vercesi. → Dipartimento di Fisica e Istituto Nazionale Fisica Nucleare Bologna F. Giorgi, M. Villa, A. Zoccoli.

FTK: Projects to Institutions 4 DF crates: cluster finding split by layer 8 “core” crates: AMboard Data Organizer GigaFitter S-links Raw data ROBs Track data ROB Track data ROB Pisa & Frascati & Fermilab the AMChip could be 3D Frascati-Waseda: Clustering in Pixels-SCT mezznines Pixels & SCT RODs Chicago GigaFitter + Data Organizer + HW Pisa: AMBoard Illinois: Final board in core crate USA-Italy “2-outHola” Fermilab: DF motherboards USA+Italy: crates + links + backplanes… 1 Readout Crate Argonne

LAMB Standard cell chip 40 MHz clock FPGA for Roads AMBoard P3 serial LVDS Control FPGA for SS Input AM0+TSP+DO+TF+HW CPU vme AM1+TSP+DO+TF +HW AM2+TSP+DO+TF +HW AM3+TSP+DO+TF +HW AM4+TSP+DO+TF +HW AM5+TSP+DO+TF +HW AM6+TSP+DO+TF +HW AM7+TSP+DO+TF +HW 11LayFit+HW AM10+….. AM11+….. AM12+….. AM13+…… AM14+….. AM8+….. AM9+…... 11LayFit+ HW final AM15+….. 11LayFit+ HW final 11LayFit+HW OPTION A AUX card Connectors for Hits LVDS Cables DO+TF+HW HWTF DO INPUT FIFOs HWTF DO HWTF DO HWTFDO Connectors for tracks output Interface SSMAP Processor Unit Pisa +Chicago ITALIAN DUTIES for 3x10**34 PISA DATA FORMATTER FRASCATI FERMILAB

THE CHALLENGING PART: THE NEW AMCHIP AND THE TSP TSP in the AUX card? Could be enough +TSP? LAMB Standard cell chip 40 MHz clock TSP In the AMBoard? Easy but expensive FPGA +TSP? In the LAMB? NOT Easy but LESS expensive AMchip TSP? Memories? In the 3D CHIP? Very challenging Very powerfull R&D NEEDED Waiting 14 Tev

Data Chamonix Shutdown Vertical Atlas + later FTK prototype on barrel Z→ bbar Z→   s   With proto-FTK Not before 2016 we will need New AMchip and TSP. At least 5 year R&D 3x10**34: Production COSTS (INCREASED) & SCHEDULE (LONGER) 1

3 x 10**34: INCREASED PROD COSTS BUT LONGER SCHEDULE 2  FRASCATI - mezzanine PRODUCTION : 250 K€ (Last July 250)  PISA - PRODUCTION AMBOARD + LAMB with TSP in AMBOARD K€ (last July 420 K€ but TSP was not included) However: 1.Phase 1 Peak luminosity recently decreased to 2,5 x10**34 2.TSP probably not necessary with optimization (14 Tev events needed) 3.IF needed it will be very far from now……at least 6 years from now ! 4.Not necessarily will be in the AMBoard……. (most expensive option) 5.Technology advancement and R&D → reduction of costs 6.We can look for extra collaborators for the TSP 7.LET’s concentrate on the cost without new AMChip and TSP  Pisa board production is back to 420 K€ ( chips+IVA) as calculated in July if no TSP.  AMchip: R&D 90 nm 3-D: first prototype 40 k€ For a planar chip: MPW 1 cm^2 : ~100 k € if 90 nm is old enough (2015) Masks whole wafer: ~200 k € (if enough old) (end 2015) Pilot run: ~30 k$ per 3k chips (we need 16k, ~50 k€, if 90 nm old!) TOT planar: 350 +IVA= 420 k€ → AND 3D??

SUMMARY GLOBAL COSTS: PRODUCTION ITALY: = 1090 k€ (like in july talk +IVA) + Prototype Development – proto-FTK – commissioning – software – services – R&D for TSP & AMchip 3D + extra TSP undefined costs STARTING 2015 BOARDSAMchip

: vertical AMboard + EDRO + 2-D clustering 2012: vertical – insertion in TDAQ using fake hits substitute some HOLAs with double output HOLAs proto-FTK: 4 Processing Unit/region (80 k€ +110 k€ + CDF LAMBs) install as much as possible new HOLAs 2013:use proto-FTK for b-tagging, tau-tagging and B Physics triggers make a decision for TSP (end R&D)→ start final developments MILESTONEs COST PROFILE IN THE NEXT YEARS for ITALY 2011: ½ production of HOLAs and fibers ~80 K€ (could September) ½ 3D R&D chip ~20 K€ prototypes & R&D TSP ~40 K€ 2012: first AMboard bunch ~ K€ services ~ 20 K€ ~50 K€ in 2010, ~140 K€ in 2011 and ~210 K€ 2012 HARD to predict more without knowing AMchip & TSP R&D results & future LHC schedule. However ~500 K€ in ~ could allow to build the 10**34 system – except TSP and AMchip

AMCHIP We are working (L.Sartori, Pisa+ M.Beretta, E. Bossini, Frascati) at the 2010 mini-asic prototype provided of full custom cell (M. Beretta Frascati) with 2 main goals: 1.Area reduction to obtain higher pattern densities 2.Power consumption reduction to be able to use large silicon areas Pattern Density/power with respect the CDF chip: 90 nm against 180 nm → factor ~4 for area and power consumption reduction (V 90 /V 180 )**2 Full custom cell: a factor 2 gain for both area and consumption. Future collaboration with Fermilab to stack 2 or 4 tiers with 3D technology

Conclusions Things run really fast TDAQ suggestions, than TP to USG in march We need Atlas Italia & INFN referee feedback before march (as soon as possible).

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