FONT4 Status Report Glenn Christian John Adams Institute, Oxford for FONT collaboration

Glenn Christian - LCABD 25/09/06 2 IP Feedback system - concept Last line of defence against relative beam misalignment Measure vertical position of outgoing beam and hence beam-beam kick angle Use fast amplifier and kicker to correct vertical position of beam incoming to IR FONT – Feedback On Nanosecond Timescales

Glenn Christian - LCABD 25/09/06 3 FONT1,2,3 Analogue Feedback Tests NLCTA: , 170 ns train length, 87 ps bunch spacing –Achieved total latency of 67 (FONT1) & 54 ns (FONT2) ATF: , 56 ns train length, 2.8 ns bunch spacing –Latency 23 ns –BPM processor resolution of 3-5 microns

Glenn Christian - LCABD 25/09/06 4 FONT1,2,3: Summary 67 ns 54 ns 23 ns

Glenn Christian - LCABD 25/09/06 5 FONT4 motivation FONT1,2,3 – ultra-fast demonstration of feedback using analogue BPM processor originally driven by ‘warm’ bunch spacing FONT4 – demonstration of feedback on ILC-like bunches using digital processor –allows implementation of algorithms for luminosity recovery Now 3 bunch train at ATF produced from ~300 ns kicker pulse Later new extraction kicker - 20 ~150 ns (FONT5?)

Glenn Christian - LCABD 25/09/06 6 FONT4 system overview KICKERBPM1BPM3BPM2 AMP Analog FE Witness BPMs Digital processor Feedback BPM Machine timing system Scopes ∑ ∆ BEAM clks, triggers LO DAQ I/O, digital DAQ

Glenn Christian - LCABD 25/09/06 7 FONT4 goals/challenges Stabilise third bunch at micron level –Require latency < bunch spacing –Nominal bunch spacing 154 ns but can be altered in 2.8 ns steps – must be able to work with this! –For this reason set latency target as 140 ns Max ADC sampling speed (14-bit device): 105 MHz –One sample per bunch – leads to rather complicated arrangement for sampling at the peak for each bunch –Need timing synchronised to machine (357 MHz machine clock, 2.16 MHz ring clock, and pre-beam trigger) –Want to sample as fast as possible (choose 357/4 MHz adjusted using 357/5 MHz between bunches)

Glenn Christian - LCABD 25/09/06 8 Digital Board 2 x Analog Input channels (single-ended) 2 x Analog Output channels (differential)4 x General-purpose digital outputs 3 x external clock/trigger inputs Xilinx Virtex4 FPGA Analog Devices ADC/DACs 40 MHz oscillator RS232 comms JTAG port PROM GP I/O Header

Glenn Christian - LCABD 25/09/06 9 FONT4 Latency Original Latency Budget Time of flight kicker to BPM (assuming 2m lever arm): 7 ns Signal propagation delay BPM to kicker: 15 ns Irreducible latency: 22 ns BPM analogue processor: 10 ns Digital processor: 68 ns –ADC/DAC: ~40 ns –FPGA I/O: 3 ns –FPGA processing (8 clock cycles): 25 ns Amplifier: 40 ns Electronics latency: ~118 ns Total latency: ~140 ns Digital board latency test Minimum latency ~6.5 clock cycles ~70 MHz

Glenn Christian - LCABD 25/09/06 10 JTAG INPUTS OUTPUTS Clk_357 Clk_2.16 Clk_40 ILA Trigger VIO controls FPGA – Timing & Data Processing CTR1 RST CTR2== SYNC_DELAY RST BRAM ADDR Trigger processing ADC_clkDAC_clk & Difference Sum 1/Sum (LUT) X X GAIN +& AOUT DELAY LOOP IDELAY

Glenn Christian - LCABD 25/09/06 11 Preliminary beam ATF (Spring 2006) Sampling –ADC/DAC sampling rate of 357/5 (71.4 MHz) continually clocked –Studied beam with bunch spacing of 154 and 140 ns –Latency ~ 92 ns incl extra cables Gain Stage Rudimentary form of ‘online’ gain variation –left bit shift to multiply by powers of 2 – up to gain of x128 –no cost to latency Overflow – wraparound No saturation built in Analogue signals Digital signals

Glenn Christian - LCABD 25/09/06 12 New Analogue Front-End Processor New PCB front-end processors designed and built – based on FONT3 processor (connectorised components) Integrated 2-channel board (sum and difference), ease-of-use (less set-up), greater reliability, simplified phasing of the local oscillator, optional amplifier mounting. Stripline Inputs Raw sum loopback LO input Difference output Sum (I) output Sum Q output

Glenn Christian - LCABD 25/09/06 13 New analogue processor – tests at ATF (Spring 2006) Resolution measured to be 3-4 microns

Glenn Christian - LCABD 25/09/06 14 New Amplifier Design New design for “universal” FONT amplifier in progress –Designed to have flexibility to meet future requirements –Design for 10 us operation with 35 ns settling time at rep rate of 2 Hz –Output current up to +/- 30 A –Currently being sourced from industry

Glenn Christian - LCABD 25/09/06 15 Oxford bench-tests Manufacture synced digital (1-bit) bunch, 2.16 MHz, and trigger on FPGA to test timing and synchronisation firmware – looped back to board inputs TriggerBunch 2.16 MHzDiagnostic

Glenn Christian - LCABD 25/09/06 16 Bench Tests Latency: 76 ns incl cable DAC output held active for 154 ns (nominal bunch spacing) New lab equipment – impulse generator to mock-up BPM stripline signals to test complete system

Glenn Christian - LCABD 25/09/06 17 Conclusions Demonstrate closed loop feedback at ATF with 3 bunches ~150ns spacing with digital feedback processor late 2006/early 2007 New front-end analogue processor built and tested New amplifier design currently in production Setting up test bench system in Oxford for exercising the complete system