Copyright ©2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey All rights reserved. Digital Fundamentals, Tenth Edition Thomas L. Floyd Figure 3.1 Standard logic symbols for the inverter (ANSI/IEEE Std ).

Copyright ©2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey All rights reserved. Digital Fundamentals, Tenth Edition Thomas L. Floyd Figure 3.2 Inverter operation with a pulse input. Open file F03-02 to verify inverter operation.

Copyright ©2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey All rights reserved. Digital Fundamentals, Tenth Edition Thomas L. Floyd Figure 3.3 Timing diagram for the case in Figure 3–2.

Copyright ©2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey All rights reserved. Digital Fundamentals, Tenth Edition Thomas L. Floyd Figure 3.4

Copyright ©2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey All rights reserved. Digital Fundamentals, Tenth Edition Thomas L. Floyd Figure 3.5

Copyright ©2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey All rights reserved. Digital Fundamentals, Tenth Edition Thomas L. Floyd Figure 3.6 The inverter complements an input variable.

Copyright ©2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey All rights reserved. Digital Fundamentals, Tenth Edition Thomas L. Floyd Figure 3.7 Example of a 1’s complement circuit using inverters.

Copyright ©2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey All rights reserved. Digital Fundamentals, Tenth Edition Thomas L. Floyd Figure 3.8 Standard logic symbols for the AND gate showing two inputs (ANSI/IEEE Std ).

Copyright ©2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey All rights reserved. Digital Fundamentals, Tenth Edition Thomas L. Floyd Figure 3.9 All possible logic levels for a 2-input AND gate. Open file F03-09 to verify AND gate operation.

Copyright ©2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey All rights reserved. Digital Fundamentals, Tenth Edition Thomas L. Floyd Figure 3.10 Example of AND gate operation with a timing diagram showing input and output relationships.

Copyright ©2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey All rights reserved. Digital Fundamentals, Tenth Edition Thomas L. Floyd Figure 3.11

Copyright ©2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey All rights reserved. Digital Fundamentals, Tenth Edition Thomas L. Floyd Figure 3.12

Copyright ©2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey All rights reserved. Digital Fundamentals, Tenth Edition Thomas L. Floyd Figure 3.13

Copyright ©2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey All rights reserved. Digital Fundamentals, Tenth Edition Thomas L. Floyd Figure 3.14

Copyright ©2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey All rights reserved. Digital Fundamentals, Tenth Edition Thomas L. Floyd Figure 3.15 Boolean expressions for AND gates with two, three, and four inputs.

Copyright ©2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey All rights reserved. Digital Fundamentals, Tenth Edition Thomas L. Floyd Figure 3.16 An AND gate performing an enable/inhibit function for a frequency counter.

Copyright ©2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey All rights reserved. Digital Fundamentals, Tenth Edition Thomas L. Floyd Figure 3.17 A simple seat belt alarm circuit using an AND gate.

Copyright ©2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey All rights reserved. Digital Fundamentals, Tenth Edition Thomas L. Floyd Figure 3.18 Standard logic symbols for the OR gate showing two inputs (ANSI/IEEE Std ).

Copyright ©2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey All rights reserved. Digital Fundamentals, Tenth Edition Thomas L. Floyd Figure 3.19 All possible logic levels for a 2-input OR gate. Open file F03-19 to verify OR gate operation.

Copyright ©2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey All rights reserved. Digital Fundamentals, Tenth Edition Thomas L. Floyd Figure 3.20 Example of OR gate operation with a timing diagram showing input and output time relationships.

Copyright ©2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey All rights reserved. Digital Fundamentals, Tenth Edition Thomas L. Floyd Figure 3.21

Copyright ©2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey All rights reserved. Digital Fundamentals, Tenth Edition Thomas L. Floyd Figure 3.22

Copyright ©2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey All rights reserved. Digital Fundamentals, Tenth Edition Thomas L. Floyd Figure 3.23

Copyright ©2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey All rights reserved. Digital Fundamentals, Tenth Edition Thomas L. Floyd Figure 3.24 Boolean expressions for OR gates with two, three, and four inputs.

Copyright ©2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey All rights reserved. Digital Fundamentals, Tenth Edition Thomas L. Floyd Figure 3.25 A simplified intrusion detection system using an OR gate.

Copyright ©2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey All rights reserved. Digital Fundamentals, Tenth Edition Thomas L. Floyd Figure 3.26 Standard NAND gate logic symbols (ANSI/IEEE Std ).

Copyright ©2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey All rights reserved. Digital Fundamentals, Tenth Edition Thomas L. Floyd Figure 3.27 Operation of a 2-input NAND gate. Open file F03-27 to verify NAND gate operation.

Copyright ©2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey All rights reserved. Digital Fundamentals, Tenth Edition Thomas L. Floyd Figure 3.28

Copyright ©2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey All rights reserved. Digital Fundamentals, Tenth Edition Thomas L. Floyd Figure 3.29

Copyright ©2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey All rights reserved. Digital Fundamentals, Tenth Edition Thomas L. Floyd Figure 3.30 Standard symbols representing the two equivalent operations of a NAND gate.

Copyright ©2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey All rights reserved. Digital Fundamentals, Tenth Edition Thomas L. Floyd Figure 3.31

Copyright ©2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey All rights reserved. Digital Fundamentals, Tenth Edition Thomas L. Floyd Figure 3.32

Copyright ©2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey All rights reserved. Digital Fundamentals, Tenth Edition Thomas L. Floyd Figure 3.33

Copyright ©2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey All rights reserved. Digital Fundamentals, Tenth Edition Thomas L. Floyd Figure 3.34 Standard NOR gate logic symbols (ANSI/IEEE Std ).

Copyright ©2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey All rights reserved. Digital Fundamentals, Tenth Edition Thomas L. Floyd Figure 3.35 Operation of a 2-input NOR gate. Open file F03-35 to verify NOR gate operation.

Copyright ©2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey All rights reserved. Digital Fundamentals, Tenth Edition Thomas L. Floyd Figure 3.36

Copyright ©2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey All rights reserved. Digital Fundamentals, Tenth Edition Thomas L. Floyd Figure 3.37

Copyright ©2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey All rights reserved. Digital Fundamentals, Tenth Edition Thomas L. Floyd Figure 3.38 Standard symbols representing the two equivalent operations of a NOR gate.

Copyright ©2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey All rights reserved. Digital Fundamentals, Tenth Edition Thomas L. Floyd Figure 3.39

Copyright ©2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey All rights reserved. Digital Fundamentals, Tenth Edition Thomas L. Floyd Figure 3.40

Copyright ©2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey All rights reserved. Digital Fundamentals, Tenth Edition Thomas L. Floyd Figure 3.41

Copyright ©2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey All rights reserved. Digital Fundamentals, Tenth Edition Thomas L. Floyd Figure 3.42 Standard logic symbols for the exclusive-OR gate.

Copyright ©2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey All rights reserved. Digital Fundamentals, Tenth Edition Thomas L. Floyd Figure 3.43 All possible logic levels for an exclusive-OR gate. Open file F03-43 to verify XOR gate operation.

Copyright ©2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey All rights reserved. Digital Fundamentals, Tenth Edition Thomas L. Floyd Figure 3.44

Copyright ©2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey All rights reserved. Digital Fundamentals, Tenth Edition Thomas L. Floyd Figure 3.45 Standard logic symbols for the exclusive-NOR gate.

Copyright ©2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey All rights reserved. Digital Fundamentals, Tenth Edition Thomas L. Floyd Figure 3.46 All possible logic levels for an exclusive-NOR gate. Open file F03-46 to verify XNOR gate operation.

Copyright ©2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey All rights reserved. Digital Fundamentals, Tenth Edition Thomas L. Floyd Figure 3.47 Example of exclusive-OR gate operation with pulse waveform inputs.

Copyright ©2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey All rights reserved. Digital Fundamentals, Tenth Edition Thomas L. Floyd Figure 3.48

Copyright ©2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey All rights reserved. Digital Fundamentals, Tenth Edition Thomas L. Floyd Figure 3.49 Typical dual in-line (DIP) and small-outline (SOIC) packages showing pin numbers and basic dimensions.

Copyright ©2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey All rights reserved. Digital Fundamentals, Tenth Edition Thomas L. Floyd Figure 3.50 Pin configuration diagrams for some common gate configurations.

Copyright ©2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey All rights reserved. Digital Fundamentals, Tenth Edition Thomas L. Floyd Figure 3.51 Logic symbols for hex inverter (04 suffix) and quad 2-input NAND (00 suffix). The symbol applies to the same device in any CMOS or bipolar series.

Copyright ©2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey All rights reserved. Digital Fundamentals, Tenth Edition Thomas L. Floyd Figure 3.52

Copyright ©2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey All rights reserved. Digital Fundamentals, Tenth Edition Thomas L. Floyd Figure 3.53 The LS series NAND gate output fans out to a maximum of 20 LS series gate inputs.

Copyright ©2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey All rights reserved. Digital Fundamentals, Tenth Edition Thomas L. Floyd Figure 3.54 The partial data sheet for a 74LS00 quad 2-input NAND gate.

Copyright ©2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey All rights reserved. Digital Fundamentals, Tenth Edition Thomas L. Floyd Figure 3.55 The partial data sheet for a 74HC00A quad 2-input NAND gate.

Copyright ©2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey All rights reserved. Digital Fundamentals, Tenth Edition Thomas L. Floyd Figure 3.55 (continued) The partial data sheet for a 74HC00A quad 2-input NAND gate.

Copyright ©2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey All rights reserved. Digital Fundamentals, Tenth Edition Thomas L. Floyd Figure 3.56 The effect of an open input on a NAND gate.

Copyright ©2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey All rights reserved. Digital Fundamentals, Tenth Edition Thomas L. Floyd Figure 3.57 Troubleshooting a NAND gate for an open input.

Copyright ©2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey All rights reserved. Digital Fundamentals, Tenth Edition Thomas L. Floyd Figure 3.58 Troubleshooting a NOR gate for an open output.

Copyright ©2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey All rights reserved. Digital Fundamentals, Tenth Edition Thomas L. Floyd Figure 3.59

Copyright ©2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey All rights reserved. Digital Fundamentals, Tenth Edition Thomas L. Floyd Figure 3.60

Copyright ©2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey All rights reserved. Digital Fundamentals, Tenth Edition Thomas L. Floyd Figure 3.61 Hippocrates.

Copyright ©2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey All rights reserved. Digital Fundamentals, Tenth Edition Thomas L. Floyd Figure 3.62 Basic concept of a programmable AND array.

Copyright ©2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey All rights reserved. Digital Fundamentals, Tenth Edition Thomas L. Floyd Figure 3.63

Copyright ©2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey All rights reserved. Digital Fundamentals, Tenth Edition Thomas L. Floyd Figure 3.64 The programmable fuse link.

Copyright ©2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey All rights reserved. Digital Fundamentals, Tenth Edition Thomas L. Floyd Figure 3.65 The programmable antifuse link.

Copyright ©2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey All rights reserved. Digital Fundamentals, Tenth Edition Thomas L. Floyd Figure 3.66 A simple AND array with EPROM technology. Only one gate in the array is shown for simplicity.

Copyright ©2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey All rights reserved. Digital Fundamentals, Tenth Edition Thomas L. Floyd Figure 3.67 Basic concept of an AND array with SRAM technology.

Copyright ©2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey All rights reserved. Digital Fundamentals, Tenth Edition Thomas L. Floyd Figure 3.68 Setup for programming a PLD in a programming fixture (programmer).

Copyright ©2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey All rights reserved. Digital Fundamentals, Tenth Edition Thomas L. Floyd Figure 3.69 Programming setup for reprogrammable logic devices.

Copyright ©2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey All rights reserved. Digital Fundamentals, Tenth Edition Thomas L. Floyd Figure 3.70 Examples of design entry of an AND gate.

Copyright ©2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey All rights reserved. Digital Fundamentals, Tenth Edition Thomas L. Floyd Figure 3.71 Simplified illustration of in-system programming via a JTAG interface.

Copyright ©2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey All rights reserved. Digital Fundamentals, Tenth Edition Thomas L. Floyd Figure 3.72 Simplified block diagram of a PLD with an embedded processor and memory.

Copyright ©2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey All rights reserved. Digital Fundamentals, Tenth Edition Thomas L. Floyd Figure 3.73

Copyright ©2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey All rights reserved. Digital Fundamentals, Tenth Edition Thomas L. Floyd Figure 3.74

Copyright ©2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey All rights reserved. Digital Fundamentals, Tenth Edition Thomas L. Floyd Figure 3.75

Copyright ©2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey All rights reserved. Digital Fundamentals, Tenth Edition Thomas L. Floyd Figure 3.76

Copyright ©2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey All rights reserved. Digital Fundamentals, Tenth Edition Thomas L. Floyd Figure 3.77

Copyright ©2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey All rights reserved. Digital Fundamentals, Tenth Edition Thomas L. Floyd Figure 3.78

Copyright ©2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey All rights reserved. Digital Fundamentals, Tenth Edition Thomas L. Floyd Figure 3.79

Copyright ©2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey All rights reserved. Digital Fundamentals, Tenth Edition Thomas L. Floyd Figure 3.80

Copyright ©2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey All rights reserved. Digital Fundamentals, Tenth Edition Thomas L. Floyd Figure 3.81

Copyright ©2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey All rights reserved. Digital Fundamentals, Tenth Edition Thomas L. Floyd Figure 3.82

Copyright ©2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey All rights reserved. Digital Fundamentals, Tenth Edition Thomas L. Floyd Figure 3.83

Copyright ©2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey All rights reserved. Digital Fundamentals, Tenth Edition Thomas L. Floyd Figure 3.84

Copyright ©2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey All rights reserved. Digital Fundamentals, Tenth Edition Thomas L. Floyd Figure 3.85

Copyright ©2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey All rights reserved. Digital Fundamentals, Tenth Edition Thomas L. Floyd Figure 3.86

Copyright ©2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey All rights reserved. Digital Fundamentals, Tenth Edition Thomas L. Floyd Figure 3.87

Copyright ©2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey All rights reserved. Digital Fundamentals, Tenth Edition Thomas L. Floyd Figure 3.88

Copyright ©2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey All rights reserved. Digital Fundamentals, Tenth Edition Thomas L. Floyd Figure 3.89

Copyright ©2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey All rights reserved. Digital Fundamentals, Tenth Edition Thomas L. Floyd Figure 3.90

Copyright ©2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey All rights reserved. Digital Fundamentals, Tenth Edition Thomas L. Floyd Figure 3.91

Copyright ©2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey All rights reserved. Digital Fundamentals, Tenth Edition Thomas L. Floyd Figure 3.92

Copyright ©2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey All rights reserved. Digital Fundamentals, Tenth Edition Thomas L. Floyd Figure 3.93

Copyright ©2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey All rights reserved. Digital Fundamentals, Tenth Edition Thomas L. Floyd Figure 3.94

Copyright ©2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey All rights reserved. Digital Fundamentals, Tenth Edition Thomas L. Floyd Figure 3.95

Copyright ©2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey All rights reserved. Digital Fundamentals, Tenth Edition Thomas L. Floyd Figure 3.96

Copyright ©2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey All rights reserved. Digital Fundamentals, Tenth Edition Thomas L. Floyd Figure 3.97

Copyright ©2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey All rights reserved. Digital Fundamentals, Tenth Edition Thomas L. Floyd Figure 3.98

Copyright ©2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey All rights reserved. Digital Fundamentals, Tenth Edition Thomas L. Floyd Figure 3.99

Copyright ©2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey All rights reserved. Digital Fundamentals, Tenth Edition Thomas L. Floyd Figure 3.100

Copyright ©2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey All rights reserved. Digital Fundamentals, Tenth Edition Thomas L. Floyd Figure 3.101

Copyright ©2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey All rights reserved. Digital Fundamentals, Tenth Edition Thomas L. Floyd Figure 3.102

Copyright ©2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey All rights reserved. Digital Fundamentals, Tenth Edition Thomas L. Floyd Figure 3.103

Copyright ©2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey All rights reserved. Digital Fundamentals, Tenth Edition Thomas L. Floyd Figure 3.104