CUHK Test and Fault-Tolerance for Timing Error Presenter: Feng Yuan

Timing is Almost “Everything” in IC Design Speed binning Better than worst case design FF D CLK Q FF CLK CLK D Timing Guardband D Setup Time Delay Probability --accurate delay testing --online timing error masking mechanism

CUHK PSEUDO-FUNCTIONAL TESTING FOR SMALL DELAY DEFECTS CONSIDERING POWER SUPPLY NOISE EFFECTS

The Challenge with Delay Testing o Causes for timing uncertainty o Static process variation o Dynamic supply voltage and temperature variation o Aging effect o Difficulties to apply delay o Small delay defects (SDD) o power supply noise (PSN) 1% supply voltage change cause 4% gate delay change in 90nm 0.9-V technology More severe with technology scaling Essential to be considered Dynamic supply voltage and temperature variation

PSN-Aware Delay Testing Method o To guarantee the worst-case scenario o Method to maximize PSN o To reduce test escape o Introduce test yield loss o To avoid undesired test yield loss o Low power testing techniques to reduce PSN o Lead to test escape At-speed scan patterns 20% slower than any functional patterns in a recent study!!! Observation: ICs in structural test mode behaves more differently from functional mode

An Example of Functional Un-testable Scan Testable Delay Fault Transition on targeted path can be activated by structural test pattern This transition can be only activated by non-functional pattern Functional Constraint

New Weapon: Pseudo-Functional Testing o To resolve the discrepancy o Generate functional-like test patterns o Functional constraint identification methods o SAT-based method o Mining+SAT strategy o Implication-based technique o Structural analysis in [Yuan, DAC’09] Identify near-complete constraints They do not consider PSN effects in delay testing  under testing How to exercise worst-case timing in functional mode during delay testing?

Layout-Aware Pseudo-Functional Delay Test Pattern Generation Flow Pseudo-functional SDD cube generation 1.Sensitize long paths 2.Avoid to involve illegal states PSN effect maximization 1.Identify relevant transitions 2.Activate them as many as possible 3.Avoid to involve illegal states

TW Comparison for 6 Paths of des Yield loss Test escape Better performance

CUHK INTIMEFIX: A LOW-COST AND SCALABLE TECHNIQUE FOR IN-SITU TIMING ERROR MASKING IN LOGIC CIRCUITS

Equivalent Circuit Construction with Approximate Logic o Definition of Approximate logic G is 1-approximation of F, if G => F (i.e., G=1 implies F=1) G is 0-approximation of F, if G => F Example: G=a+b is the 1-approximation of F=a+b+acb This circuit has following properties It is logically-equivalent with the original circuit F 1.1. Worst case delay is dominated by G0 and G1, when they are working 2.2.

Basic Idea All circuit’s inputs Approximated inputs Timing critical inputs

Masking Timing Error with Approximate Logic Launched value Essential side-input value

Overall Flow Timing information & netlist Identifying Critical Flip-Flop Extracting Primary Critical Segment Merging Primary Critical Segment Inserting Approximate Logic Multiple critical paths can be processed concurrently FF To reduce the hardware cost

Experimental Result Original standard deviation: 0.39 Our standard deviation: 0.19

CUHK QUESTION TIME Presenter: Feng Yuan