Electrical Characteristics of Logic Gates

Slides:

Advertisements

Similar presentations

CMOS Logic Circuits.

Advertisements

Ch 3. Digital Circuits 3.1 Logic Signals and Gates (When N=1, 2 states)

Lecture No. 7 Logic Gates By: VISHAL JETHAVA.

TTL (Transistor Transistor Logic).  Transistor Transistor logic or just TTL, logic gates are built around only transistors.  TTL was developed in 1965.

Digital Electronics Logic Families TTL and CMOS.

Logic Families and Their Characteristics

Ch 11 Bipolar Transistors and Digital Circuits

Electrical and Timing Characteristics of Standard Logic Gates (Lecture #2) ECE 331 – Digital System Design.

ISLAMIC UNIVERSITY OF GAZA Faculty of Engineering Computer Engineering Department EELE3321: Digital Electronics Course Asst. Prof. Mohammed Alhanjouri.

Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc. C H A P T E R 13 CMOS Digital Logic Circuits.

CMOS gates Electrical characteristics and timing TTL gates

Voltage Transfer Characteristic for TTL

3.4 Bipolar Logic 1. Diode Logic

Fig Operation of the enhancement NMOS transistor as vDS is increased

Physical States for Bits. Black Box Representations.

EE365 Adv. Digital Circuit Design Clarkson University Lecture #5

3.3 CMOS Logic 1. CMOS Logic Levels NextReturn Logic levels for typical CMOS Logic circuits. Logic 1 (HIGH) Logic 0 (LOW) Undefined Logic level 5.0V 3.5V.

Electrical and Timing Characteristics of Standard Logic Gates (Lecture #2) ECE 301 – Digital Electronics.

ECE 331 – Digital System Design Electrical Characteristics of Logic Gates, Circuit Design Considerations, and Programmable Logic Devices.

© 2000 Prentice Hall Inc. Figure 6.1 AND operation.

Logic Families Introduction.

Digital Integrated Circuits© Prentice Hall 1995 Inverter THE INVERTERS.

EET 252 Unit 2 Integrated Circuit Technologies

Digital logic families

ECE 331 – Digital System Design Power Dissipation and Propagation Delay.

Practical Aspects of Logic Gates COE 202 Digital Logic Design Dr. Aiman El-Maleh College of Computer Sciences and Engineering King Fahd University of Petroleum.

CSET 4650 Field Programmable Logic Devices

EET 1131 Unit 9 Logic Families

CSET 4650 Field Programmable Logic Devices Dan Solarek Logic Families Introduction & Overview.

Digital Devices. Implementing logic circuits Shorthand notation Electrical characteristics.

INTEGRATED CIRCUIT LOGIC FAMILY

Chapter 10 Digital Integrated Circuits

CH111 Chapter 11 CMOS and TTL Circuits By Taweesak Reungpeerakul.

Logic Families and Their Characteristics

Digital Logic Families PHYS3360/AEP3630 Lecture 26 1.

Ch 10 MOSFETs and MOS Digital Circuits

Electrical Characteristics of ICs Technician Series.

Electrical Characteristics of Logic Gates Dr. Ashraf Armoush © 2010 Dr. Ashraf Armoush.

Contemporary Logic Design Multi-Level Logic © R.H. Katz Transparency No. 5-1 Chapter # 2: Two-Level Combinational Logic Section Practical Matters.

Practical Digital Design Considerations Part 1 Last Mod: January 2008 ©Paul R. Godin.

Integrated Circuit Logic Families. Outline  Integrated Circuit Logic Families.

Electrical Characteristics Practice Problems 1 Last Mod January 2008  Paul R. Godin with Solutions.

ECE 331 – Digital System Design Constraints in Logic Circuit Design (Lecture #13) The slides included herein were taken from the materials accompanying.

Practical Digital Design Considerations Review of Concepts Created February 2008 ©Paul R. Godin.

1.0 INTRODUCTION  Characteristics of the active electronic components that determine the internal construction and operation of electronic circuitry.

Chapter 11 Logic Gate Circuitry.

Outline Introduction CMOS devices CMOS technology CMOS logic structures CMOS sequential circuits CMOS regular structures.

Physical States for Bits. Black Box Representations.

IC Logic Families Wen-Hung Liao, Ph.D.

1 Transistors, Boolean Algebra Lecture 2 Digital Design and Computer Architecture Harris & Harris Morgan Kaufmann / Elsevier, 2007.

Electrical Characteristics of IC’s

Digital Integrated Circuits A Design Perspective

1. Digital cmos.2 10/15 Figure 10.1 Digital IC technologies and logic-circuit families. Digital IC Technologies CMOS & Pass Transistor Logic dominate.

Counters 2.1 MSI Counters Counter ICs ©Paul Godin Updated Aug 2013 gmail.com.

Solid-State Devices & Circuits

Electrical Characteristics of ICs Part 3 Last Mod: January 2008  Paul R. Godin.

Electrical Characteristics of IC’s Part 2

EE415 VLSI Design THE INVERTER [Adapted from Rabaey’s Digital Integrated Circuits, ©2002, J. Rabaey et al.]

CH31 Chapter 3 Logic Gates By Taweesak Reungpeerakul.

Topic 1 Topic 1 Objectives Topic 2 Topic 2 Topic 3 Topic 3 Topic 4 Topic 4Menu.

Electrical Characteristics of Logic Gates Gate Characteristics Last Mod: January 2008  Paul R. Godin.

Physical Properties of Logic Devices Technician Series Created Mar

Objective Describe the specification of the various logic ICs with emphasis on fan-in, fan-out, input and output characteristic. Verify the common technical.

MAHATMA GANDHI INSTITUTE OF TECHNICAL EDUCATION & RESEARCH CENTER NAVSARI - Patel Richa ( )

Basic Digital Logic: X-OR and X-NOR Gates

Electrical Characteristics Practice Problems #1

Electrical Characteristics Practice Problems 1

Electrical Calculations

Presentation transcript:

Electrical Characteristics of Logic Gates Presentation #4: Interfacing TTL and CMOS Mod January 2008 Paul R. Godin

Interfacing CMOS and TTL Although CMOS and TTL device families have different electrical characteristics, they can be interfaced. Fanout and Noise Margin are characteristics that must be accounted for in the design process. Propagation delay and power are other important considerations.

CMOS TO TTL

CMOS TTL Noise Margin Calculation CMOS 4011B: VOH: 4.95 V VOL: 0.05 V TTL 74LS04 VIH: 2V VIL: 0.8V

CMOS TTL Noise Margin Calculation CMOS 4011B: VOH: 4.95 V VOL: 0.05 V TTL 74LS04 VIH: 2V VIL: 0.8V

CMOS TTL Noise Margin Calculation With a VnH of +2.95V and a VnL of +0.75V, there are no noise margin problems with this circuit design. Minimum=4.95V CMOS Minimum=2.0V TTL Maximum=0.8V Maximum=0.05V Output Input

CMOS TTL Fanout Calculation CMOS 4011B: IOH: -0.51mA IOL: 0.51mA TTL 74LS04 IIH: 20A IIL: -0.4mA

CMOS TTL Fanout Calculation Worst-case = 1 gate input

CMOS TTL Fanout Calculation Most CMOS devices can drive at least 1 TTL input from either the voltage or current perspective. Read the introduction in the specification sheet for the CMOS device.

TTL to CMOS

TTL CMOS Noise Margin Calculation TTL 74LS04 VOH: 2.7V VOL: 0.5V CMOS 4011B: VIH: 3.5 V VIL: 1.5 V

TTL CMOS Noise Margin Calculation TTL 74LS04 VOH: 2.7V VOL: 0.5V CMOS 4011B: VIH: 3.5 V VIL: 1.5 V Voltage Problem

TTL CMOS Noise Margin Calculation There is a problem with the noise margin. Minimum=3.5V CMOS Minimum=2.7V TTL Maximum=1.5V Maximum=0.5V Output Input

TTL CMOS Noise Margin Problem The VOH of the TTL gate is too low for the CMOS gate to reliable determine a high input.

In-Class Discussion Interface Circuits: Improve Current Improve Noise Margin Shift Voltages Switch Loads Operate with positive and negative logic Dealing with LED Loads (review)

Conclusion When mixing logic families, it is important to: review the specification sheets make the necessary calculations to ensure the devices will function properly utilize interfacing devices if needed

Review Questions What is the difference between: How do we determine: Loading and Sinking inputs Driving and Sourcing inputs Fanout and Noise Margin ICC and ICCH IDD and IT How do we determine: Fanout IC Power Consumption Noise Margin

End Paul R. Godin prgodin @ gmail.com