sPHENIX Silicon Tracker 2015/07/10 Radiation Lab meeting Y. Akiba (RIKEN)

Reference design and requirements |  |<1 and  High efficiency & purity in central Au+Au to measure modified FF High rate (15kHz DAQ) High momentum resolution to separate Upsilon states Precision vertex measurement for heavy flavor measurements (D, B  J/Psi, b-tagged jets) Compact (Fit inside of EMCAL) J.Nagle LPR talk

This 7 layer baseline design was implemented in GEANT4 simulation to evaluate the performance of the tracker Simulation shows that this design can separate the three Upsilon states Much room for design optimization (performance, cost, etc) Reference Design & Performance A. Frawley DOE review 2015/04/30 Reconfiured VTX S0a/b S1a/b S2

Concept of S2 sensor (for SVX4) 96mmx92.16mm active area Divided into 12x12 blocks Each block is 8mm x 7.68mm and made of 128 strips of 8mm x 60 micron Upper 6 bocks are connected upwards. Lower 6 blocks are connected by downwards 24 SVX4 chips to read- out the entire sensor

sPHENIX silicon tracker R&D in Japan Silicon sensor R&D at RIKEN in JFY2014 Large Prototype sensor for the outer most layer – 96 mm x 92.16mm active area – 320  m thick – AC coupled – 6x128x24 mini-trips (60  m x 8mm) – 128x24 read-out channels 5 sensors manufactured at Hamamatsu and delivered to RIKEN in March 2015 For all of 5 delivered sensors – No NG channels or strip – Vfd = 50 V – Vbreakdown > 250V (>500V for two) All 5 sensors are now at BNL for testing

I-V, C-V data Vfd: 50V No NG channels Breakdown V > 250V

Silicon tracker model for 2 nd round of R&D FPHX chip for read-out. – FPHX is the read-out chip of FVTX – 128ch/chip. 3bit ADC /ch. – Low power (64mw per chip) 5 strip layers + 2 pixel S2: 1 strip layer at R~60 cm ~1% X0 (2% in ref. design) S1ab: 2 strip layer at R~34 cm ~1% X0 total (2% in ref. design) S0ab: 2 strip layer at R~ 8 cm ~1% X0 total (2.7% in ref. design) P1: pixel at R~5 cm (reconfigured VTXP) 1.3% X0 P0: pixel at R~2.5cm (reconfigured VTXP) 1.3% X0 – All strips are 60  m x 9.6mm. S0b has a small stereo angle. – Overall material is ~5.6% radiation length. – Air cooling to achieve small radiation length – Small rad. length enables smaller over-all size and to keep the required momentum resolution to separate 3 Upsilon states – S0+S1+S2: ~8m 2 of silicon and 3.2M ch

3 sensors for strip layers Each sensor is divided in cells of 9.6m(z)x7.68mm active area. Each cell consists of 128 strips of 60  m x 9.6mm S2, S1, S0 sensors are made of 12x10, 6x10, and 2x10 cells, respectively 1 ch in S2 read 6 strips and 1 ch in S1 read 3 strips to save channel counts. Channel occupancy is ~0.2% in S1 and 0.1% in S1 in central Au+Au. Bonding pads for 10 FPHXs S2 sensor Bonding pads for 10 FPHXs S1 sensor Bonding pads for 10 FPHXs

Concept of FPHX based module (S1) This is a concept of a sensor module with FPHX read-out It is made of – Sensor of (6 x 10) cell structure. Each cell has 128ch of 80um x 9.6mm strips – A “ROC” (or “HDI”) of 10 FPHX chips. They are attached at the top and the bottom of the sensor – The “ROC” is electrically equivalent to the “small HDI” of FVTX so that it can be read- out by a FVTX test bench ROC of 10 FPHX chip

Prototype ladder A full size ladder requires many SMs. Perhaps ~half ladder for S1 and S2 is a realistic goal? ROC or Hybrid Silicon SensorSVX4 Support/cooling S1a/b ladder (double layer) S2 ladder (single layer)

Concept of S1 barrel (middle layer) 4.6cm active area; 6.4cm total (9mm wings) 44 ladders. (22 at R=30.8+/-1.0; 22 at R=33.1+/-1.0

Plan and status of 2 nd round R&D in Japan Plan: – Develop prototype S1 sensor (~5cm x 10cm, 2 sensors per wafer) at Hamamatsu – Develop read-out FPC for the sensor. – Assemble them into prototype sensor module – Test and evaluate the silicon module using FVTX test bench – About half year for the full cycle of R&D – Design and protoype of the mechanical support /cooling structure – 2 nd round of sensor module prototype in the later half of the year Goal: Protype of a full ladder at the end of JFY Status: – Started design of prototype S1 sensor at Hamamatsu. I expect that the sensor prototype will be delivered in September – Started design of read-out FPC at a FPC company near Tokyo with consultation with a wire-bonding and assembly firm. I expect that FPC will be availabe by the delivery of the sensor – Starting the mechanical/cooling design (very preliminary stage)

HPK design of S1 sensor Received from HPK today (2015/06/16)

R&D status and plan Sensor: HPK – Conceptual design done. (prevous slides) Flexible Printed Circuit: YAMASHITA Materials – Visit the company on 6/2 for discussion (YA, Nakagawa, Mitsuka, Taketani, Nagashima) – Layout design is on going – Rough cost estimate Wire-bonding/Assembly: HAYASHI – Discussion at RIKEN on 6/4 – Rough cost estimate for prototyping Goal of the first round of prototype: – both of the sensor and FPC by this fall (3months) – Assembly at Hayashi (1 month) – Test the module at RIKEN using the FVTX test bench (1month) Start / order the 2 nd round prototype in this JFY

Recent progress 1 st round of FPC layout (6 layers) by Yamshita Expected Upsilon mass resolution (calculated by Tony Frawley) 100 MeV with 65cm maximum radius

Effort for non-US funding for the tracker I submitted a large KAKENHI grant proposal to JSPS last October – JSPS is the main funding agency in Japan. Its function is similar to NSF in the US Grant Title: sPHENIX experiment: study of quark gluon plasma by using jet probes The grant asked for total of 5 oku yen (~$5M) over 5 years from JFY2015 to JFY2019. – The end date of JFY2019 is March 2020 ~ end of sPHENIX construction – In the JSPS grant system, we receive the full amount of the allocated fund. Overhead will be provided separately. The grant passed the first stage of selection and we went to a hearing on March 26. – About 20% of applicants can go to a hearing. Half of them are approved. Unfortunately, my proposal was not accepted after the hearing. I will try again this year.

Summary sPHENIX silicon tracker concept and requirements First prototype sensor delivered. – Very good result, according to the test by HPK Plan and status of the 2 nd round R&D – Use FPHX chip to reduce heat load  thinner tracker – Develop prototype sensor modules in ~half year and a prototype ladder in ~1 year – Design of sensor and FPC started.