VFE & PCB Status & schedule of production Presented by Julien Fleury Christophe de La Taille, Julien Fleury, Gisèle Martin-Chassard

Plan Measurement result on FLC_PHY1 - Linearity & dynamic range - Pedestal dispersion & noise Introducing the new FLC_PHY2 front end chip - General presentation - The new charge preamplifier - The new shaper - The new track & hold Schedule of the front-end electronic group -Front-end chip & PCB schedule

Meas. Results – linearity & dyn. range Linearity measured : -Preamplifier linearity.………………………….0.1% -Direct shaper output linearity……………….0.3% -Multiplexed output ……………………………….0.2% SimulationMeasurement Dynamic range : -Measured.………………………….3.5 pC (550 MIP) -Simulated……………………………4.2 pC (650 MIP)

Meas. Results – Pedestal disp & noise Settling time Pedestal dispersion Pedestal dispersion measured : -Average.………………………………-3.129V -Standard deviation……………….5mV -Excursion …………………………….17mV Noise measured : -C line.……………………………………..80pF -Peaking time…………………………200 ns -Measured noise ……………………2200e -

Meas. Results – Conclusion FLC_PHY1 reachs expectation for physics prototype Noise Linearity Dyn.range

New FLC_PHY2 – General presentation FLC_PHY1 FLC_PHY2 Preamp  16 gains (0.2, 0.4, 0.8, 1.6pF switchable) Lower noise (input trans improved) Shaper  bigain differential track & hold  differential Preamp  1 gain (1.5pF) Low noise (2200e - ) Shaper  Mono gain unipolar track & hold  Unipolar Pin-Pin compatibility Amp OPA MUX out Gain=1 MUX out Gain=10 1 channel

New FLC_PHY2 – charge preamp Characteristics 4 switchable feedback capa Max out from 80  1300 MIP input PMOS size increased  noise reduced pF 0.4pF 0.8pF 1.6pF 1pF 2pF 4pF Hardware configuration  No modification of the read-out interface  Gain switches driven on VFE board

New FLC_PHY2 – shaper Filter structure stays (CRRC) High gain amplifier is replaced by an OP AMP  Differential structure makes the pedestal dispertion lower The OP AMP have been designed and layouted in LAL (used in OPERA slow shaper) C1 R1 C2 R2 C1 R1 C2 R2 - + Old version New version

New FLC_PHY2 – shaper Peaking time is 200ns on both gain High-gain shapers can be shut down by switching off their biases Two different output for low gain and high gain  Interface compatibility with the read out is kept New interface not written at this point Linearity simulation Transcient simulation

New FLC_PHY2 – track & hold Including a Widlar structure (differential) to reduce pedestal dispersion Common collector buffer structure is kept for safety Memory capacitance is increased from 1 to 2pF

New FLC_PHY2 – Conclusion Pin to pin compatibility with FLC_PHY1  to simplify PCB design Read out interface compatibility with FLC_PHY1  R&D on the front end chip has no influence on PCB and RO development Amp OPA MUX out Gain=1 MUX out Gain=10 1 channel

Schedule – Front end chip & PCB FLC_PHY1 FLC_PHY2DesignFoundry April, 7 th June, 23 rd Test Sept. Test Choice Standby Production November PCBDesignFab Test Production GOAL : Be ready for cosmics test in february 2004  Build VFE boards in January 2004 Week 15 : Fake pcb for mech. Week 23 : Drawing of PCB V2 Week 23 : Drawing of test prod. board