Analog Trigger for CTA MST CTA MST Trigger & Integration Meeting Berlin, 7 November 2011 Luis A. Tejedor on behalf of GAE-UCM, IFAE & CIEMAT groups 1

Outline Concept Architecture – Level 0 – L0 fanout – Level 1 – Distribution Colibri implementation Tests 2

Analog Trigger Concept Concept: – Excess of signal localized in a small region in a few nanoseconds time window. Two possible approaches: – Majority trigger: excess of the number of pixels with a signal above a threshold in definite regions. – Sum trigger: excess of the analog clipped sum of the signals in the pixels in definite regions of a given size. Features: – Reduce Night Sky Background (NSB) accidentals – High efficiency for gamma-like events – Latency: less than analog memories depth (~200 ns)  Dead time negligible. – Power, weight and cost – Compatible with Nectar and Dragon readouts – Flexibility to configure the thresholds and choose one among 3 possible trigger region sizes by software, in an easy way. 3

Analog Trigger Concept Each hexagon represents a cluster: 7 packet pixels The Level 0 trigger first combines the signal within a cluster to provide a L0 signal (Majority or Sum trigger) Then the Level 1 decision combines the L0 signals among all closed packet patches of 2, 3 or 4 clusters If the combination exceeds a certain threshold in any patch, the camera is triggered The trigger is distributed to all clusters isochronously 4

Sum Trigger Features While majority schemes only consider two possible states for the pixels (below or above the threshold), analog sum trigger use all the information in the pulse. For this reason, it has a good performance, specially for low energies. To take the most of this advantage avoiding instabilities it requires to be configured always with the appropriate threshold. 5 Implementing an automatic threshold control with current CTA purposed hardware is straightforward and no more electronic components are required. MAGIC telescope use sum trigger and automatic threshold control nowadays, with good results. It was used, for example, to detect Crab pulsar at 25 GeV.

Analog Trigger Architecture Common implementation for LST, MST and SST Four different modules: – Level 0 (majority/sum): process the analog signals of the 7 pixels in a cluster – L0 fanout: Replicates de L0 output to export it to the neighbor clusters – Level 1 decision: process the L0s of a certain number of clusters (2, 3 or 4) – L1 distribution: Distributes L1 outputs to all clusters in the camera. 6 Level 0 decision within cluster (7 pixels) Σ Vth Sing2diff Level 1 decision: sum of L0’s L1 distribution: provide L1 to all clusters in the camera (+ central trigger interface) 1/cluster L0 fanout: provide L0 to neighbor clusters Majority trigger: L1 trigger (camera Trigger) Sum trigger:

Analog Trigger Architecture 7 Architecture (subsystems): Level 0 decision: IFAE Level 0 fanout: UCM-GAE Level 1 decision: UCM-GAE Level 1 distribution: CIEMAT L0 fanout Cluster pixels L1 Dist rib DAQ FPGA 1-Cluster diagram: L0 fanout Cluster pixels L1 Dist rib DAQ FPGA L0 fanout Cluster pixels L1 Dist rib DAQ FPGA L0 fanout Cluster pixels L1 Dist rib DAQ FPGA Front-end Backplane Front-end Backplane Analog trigger stages

Level 0: Concept and Interfaces It process the analog signals from the seven pixels in a cluster: – In the sum trigger approach it performs the analog sum of the scaled and clipped analog inputs. – In the majority trigger it compares every input with a threshold, makes the analog sum of the outputs and gives an output with 8 possible levels. It is placed in the front-end board of every cluster. Interfaces: – Seven differential analog inputs, 100 Ω differential impedance, 1.2 V maximum differential amplitude. – One differential analog output, same characteristics as the inputs. – 3 control lines for an SPI interface to configure the thresholds in a DAC with 7 outputs (Majority) or – 6 lines for 2 SPI interfaces to control 2 DACs, one for attenuators, and other for clipping stage (Sum trigger). – ± 3.3 V power supply. 8

Level 0: Modules 9 Level 0 Majority Sum

L0 fanout: Concept There is one per cluster and it is placed between the backplane and the trigger distribution board. It replicates the output from the Level 0 of its cluster to export it to the neighbors. It also collects the Level 0 signals from the neighbors and sends them to the Level 1. It lets other signals to go through it, to the distribution board or to a digital trigger board, transparently. 10

L0 fanout: Interfaces Interface with backplane One analog differential input with the L0 output of the cluster. 6 analog differential outputs, with the L0 outputs of the neighbor clusters (not all required), and the cluster itself, once replicated. 10 digital LVDS differential pairs for digital inputs. One of them used for inputs from L1 decision to distribution board. 11 digital LVDS differential pairs for digital outputs. One of them used also for outputs from distribution to readout board. ±3.3 V power supply Interface with distribution board 11 digital LVDS differential pairs for digital inputs. One of them used also for trigger inputs from distribution board, once distributed. 10 digital LVDS differential pairs for digital outputs. One of them used for signals from L1 decision to distribution board V power supply. 11 Interface with neighbor L0 fanouts 5 input analog differential pairs to import L0s from neighbors. 5 output analog differential pairs to export L0 to neighbors.

12 Cluster L0 plus L0’s from all neighbors (except for #4) are taken into account for L1 decision Several operation modes for different trigger region sizes: Mode 4: performs only 3 sums of 4 clusters Mode 3: performs only 2 sums of 3 clusters Mode 2: performs only 3 sums of 2 clusters Result is compared with threshold, L1 trigger activation if any of the sums is above the threshold With this connection scheme, complete overlapping in the camera is obtained L1 Decision: Concept

13 L1 Decision: Modules and Interfaces 6 analog differential inputs, with L0s from the cluster itself, and from neighbors. 3 digital inputs for SPI interface, to control the thresholds in the DAC. 2 digital inputs to select the working mode. 1 differential LVDS digital output, with trigger decision. Routed to L1 Distribution board through DAQ FPGA, backplane and L0 fanout.

14 The goal is to collect L1 decision outputs from all clusters and provide L1 trigger to all cluster DAQ boards in the camera Characteristics: Asynchronous propagation of trigger pulse (not synchronized with clock) Event time information encoded in trigger pulse leading edge Very low time dispersion in trigger arrival time among clusters (delay equalization ) and low jitter Trigger latency compatible with analog memories depth FPGA-based distribution modules 1 distribution module/cluster Each module is provided with a LVDS trigger signal from L1 decision module Each module is connected only to its next neighbors The trigger pulse is routed depending on the position in the camera in order to reach all clusters Each module provides the trigger pulse to the cluster DAQ FPGA Trigger Connection among Clusters: Trigger Distribution diagram: L1 Distribution: Concept

15 L1 Distribution: Modules and Interfaces 1 LVDS differential digital input with the output from L1 Decision 1 LVDS differential digital output with the L1 trigger signal, once distributed V Power Supply Interface with L0 fanout: Interface with neighbor L1 distribution boards: 6 LVDS differential digital inputs to receive propagated trigger signals from neighbors. 6 LVDS differential digital outputs to propagate trigger to neighbors.

16 Always triggering with all the clusters of the camera is not efficient. Autonomous cluster trigger improves that efficiency, but fixing its threshold is tricky: Higher thresholds imply losing events Lower thresholds imply capturing too much noise Solution (Colibri scheme): two different trigger levels for Low level trigger: Tagging regions of interest (ROI): S1 High level trigger: Taking the decision to read them: S2 Earliest triggers must be delayed to compensate the propagation time in all the camera Allows triggering with time sliding windows for large energy showers From C. Lindsay Naumann Autonomous Cluster Trigger (Colibri): Concept

Colibri: Hardware changes Implementing the Colibri implies several hardware changes: Level 0 boards remain unchanged. Level 1 decision module have to compare with 2 thresholds. 2 Level 1 signals, from L1 decision to the DAQ FPGA have to be routed in the front-end board. Between this FPGA and the distribution board, they can use two of the digital inputs/outputs already existing, for digital trigger. L1 distribution has to propagate high level trigger and delay low level trigger signals to synchronize them. 17

L1 decision for Colibri 18 DAC AD5060 changed by AD5663R, with two outputs. No more control lines required. Three more comparators and other OR gate.

L1 Trigger Distribution for Colibri Trigger distribution in the camera for Colibri scheme has been implemented in standard L1 distribution modules, with only software changes High level trigger: Distributed to all clusters in the camera Used as “gate” for Low level trigger. “Gate” time width is a parameter. Coarse timing, 10ns resolution Distribution latency ~ 200ns If more than one cluster gives HL trigger, they are OR-ed in the distribution logic Low level trigger: No distributed to all clusters, may be distributed to neighbors. If it were required to distribute it to neighbors, two additional lines, to and from every neighbor would be necessary. Fine timing, 25ps resolution Trigger to FE FPGA for a given cluster is the coincidence between the OR of all High Level triggers and the particular Low Level trigger of the cluster 19

L1 Trigger Distribution for Colibri 20 Distribution logic: Distribution of HL trigger to neighbors Reception of triggers from neighbors All HL triggers are OR-ed Shift Register Local High Level Trigger (from L1 decision Module) Shift register: configurable delay for each node: 0 ~ 100ns each register Coarse resolution (~ 10ns, register clocked with 100MHz) The goal is to equalize the delay in all clusters. Each cluster load a different delay in the shift registers depending on its position in the camera. Distribution logic HL trigger from/to all other clusters in the camera High resolution delay Local Low Level Trigger (from L1 decision module) Fix delay in each cluster: Delay value: 200ns Fine resolution (25ps) Accurate timing w.r.t. input trigger Trigger to DAQ In the coincidence logic, the HL signal is used as a gate (enable). The LL signal is used as the real trigger (good timing) In case of multiple triggers the gate (HL signal) is updated, so the only trigger dead time is defined by the LL signal pulse time width. Shift Register AND

Tests Level 0, Level 1 Decision and Level 1 Distribution modules have already been tested alone and connected together, for standard versions. IFAE group has developed a trigger integration board to perform more complete tests with the Colibri versions of the boards and also with L0 fanout. Tests with Dragon Japan readout are taking place since first days of October in Japan. 21 Tests with Nectar are foreseen for the following weeks.

22 Possibility for next prototype: Trigger Distribution backplane, L0 fanout + L1 distribution Interconnection of backplanes with flex cabling integrated in PCB: Good signal integrity Save a lot of connectors PCB Kapton cable: Connector min. 4 differential pairs: L0 in, L0 out, L1 in, L1 out Additional signals for tagging ROIs and/or Colibri A future improvement