Modified by S. J. Fritz Spring 2009 (1) Based on slides from D. Patterson and www-inst.eecs.berkeley.edu/~cs152/ COM 249 – Computer Organization and Assembly Language Chapter 7 Multicores, Multiprocessors

Modified by S. J. Fritz Spring 2009 (2) Chapter 7 Multicores, Multiprocessors, and Clusters

Modified by S. J. Fritz Spring 2009 (3) Chapter 7 — Multicores, Multiprocessors, and Clusters — 3 Introduction Goal: connecting multiple computers to get higher performance –Multiprocessors –Scalability, availability, power efficiency Job-level (process-level) parallelism –High throughput for independent jobs Parallel processing program –Single program run on multiple processors Multicore microprocessors –Chips with multiple processors (cores) §9.1 Introduction

Modified by S. J. Fritz Spring 2009 (4) Hardware and Software Hardware Future increases in performance will come from more processors per chip, instead of higher clock rates and improved CPI (because of power limitations). Processors are called cores number expected to double every two years Multicore Processors Software Programmers must become parallel programmers, since sequential programs are slow

Modified by S. J. Fritz Spring 2009 (5) Chapter 7 — Multicores, Multiprocessors, and Clusters — 5 Hardware and Software Hardware –Serial: e.g., Pentium 4 –Parallel: e.g., quad-core Xeon e5345 Software –Sequential: e.g., matrix multiplication –Concurrent: e.g., operating system Sequential/concurrent software can run on serial/parallel hardware –Challenge: making effective use of parallel hardware as number of chips grow

Modified by S. J. Fritz Spring 2009 (6) Chapter 7 — Multicores, Multiprocessors, and Clusters — 6 What We’ve Already Covered §2.11: Parallelism and Instructions –Synchronization §3.6: Parallelism and Computer Arithmetic –Associativity §4.10: Parallelism and Advanced Instruction- Level Parallelism §5.8: Parallelism and Memory Hierarchies –Cache Coherence §6.9: Parallelism and I/O: –Redundant Arrays of Inexpensive Disks

Modified by S. J. Fritz Spring 2009 (7) Chapter 7 — Multicores, Multiprocessors, and Clusters — 7 Parallel Programming Parallel software is the problem Need to get significant performance improvement –Otherwise, just use a faster uniprocessor, since it’s easier! Difficulties –Partitioning –Coordination –Communications overhead §7.2 The Difficulty of Creating Parallel Processing Programs

Parallel Programming Parallel Programming or Parallel Software –Means either sequential or concurrent software running on parallel hardware Shared memory processors Clusters Multithreading SIMD and Vector – run sequential applications on parallel hardware Graphics processing Unit (GPU) Modified by S. J. Fritz Spring 2009 (8)

Difficulties Main difficulty is not the hardware Difficult to write or rewrite software to use multiple processors to complete one task faster Increased difficulty with increasing number of processors Modified by S. J. Fritz Spring 2009 (9)

Why So Difficult? Analogy of 8 reporters all trying to write a story and hoping to do so 8 times faster. Task must be broken into 8 equal sized pieces, otherwise some reporter are idle while those with larger tasks finish. Communication problem takes time to coordinate. Similarly, parallel programming requires scheduling, load balancing, synchronization and communication. Modified by S. J. Fritz Spring 2009 (10)

Speed-up Challenge Suppose you want to achieve a speed-up of 90 times faster with 100 processors. What percentage of the original computation can be sequential? Amdahl’s law reminds us that even small parts of a program must be done in parallel if the program is to use multiple cores efficiently. Modified by S. J. Fritz Spring 2009 (11)

Modified by S. J. Fritz Spring 2009 (12) Chapter 7 — Multicores, Multiprocessors, and Clusters — 12 Amdahl’s Law Sequential part can limit speedup Example: 100 processors, 90× speedup? –T new = T parallelizable /100 + T sequential – –Solving: F parallelizable = Need sequential part to be 0.1% of original time

Bigger Challenge Suppose you want to perform two sums: – sum of 10 scalar variable –Matrix sum of pa pair of 2-D arrays, with dimensions of 10 by 10 What speed-up do you get with 10 processors? 100 processors? What if the matrices grow to 100 by 100? Modified by S. J. Fritz Spring 2009 (13)

Modified by S. J. Fritz Spring 2009 (14) Chapter 7 — Multicores, Multiprocessors, and Clusters — 14 Scaling Example Workload: sum of 10 scalars, and 10 × 10 matrix sum –Speed up from 10 to 100 processors Single processor: Time = ( ) × t add 10 processors –Time = 10 × t add + 100/10 × t add = 20 × t add –Speedup = 110/20 = 5.5 (55% of potential) 100 processors –Time = 10 × t add + 100/100 × t add = 11 × t add –Speedup = 110/11 = 10 (10% of potential) Assumes load can be balanced across processors

Modified by S. J. Fritz Spring 2009 (15) Chapter 7 — Multicores, Multiprocessors, and Clusters — 15 Scaling Example (cont) What if matrix size is 100 × 100? Single processor: Time = ( ) × t add 10 processors –Time = 10 × t add /10 × t add = 1010 × t add –Speedup = 10010/1010 = 9.9 (99% of potential) 100 processors –Time = 10 × t add /100 × t add = 110 × t add –Speedup = 10010/110 = 91 (91% of potential) Assuming load balanced

Modified by S. J. Fritz Spring 2009 (16) Chapter 7 — Multicores, Multiprocessors, and Clusters — 16 Strong vs Weak Scaling Strong scaling: problem size fixed –As in example Weak scaling: problem size proportional to number of processors –10 processors, 10 × 10 matrix Time = 20 × t add –100 processors, 32 × 32 matrix Time = 10 × t add /100 × t add = 20 × t add –Constant performance in this example

Balancing the Load To achieve speed-up of 91 on previous problem with 100 processors, we assumed the load was perfectly balanced- each processor had 1% of the work What happens to the speed up if a processor has 2% or 5% of the work? Modified by S. J. Fritz Spring 2009 (17)

Modified by S. J. Fritz Spring 2009 (18) Chapter 7 — Multicores, Multiprocessors, and Clusters — 18 Shared Memory SMP: shared memory multiprocessor –Hardware provides single physical address space for all processors –Synchronize shared variables using locks –Memory access time UMA (uniform) vs. NUMA (nonuniform) §7.3 Shared Memory Multiprocessors

Modified by S. J. Fritz Spring 2009 (19) Chapter 7 — Multicores, Multiprocessors, and Clusters — 19 Example: Sum Reduction Sum 100,000 numbers on 100 processor UMA –Each processor has ID: 0 ≤ Pn ≤ 99 –Partition 1000 numbers per processor –Initial summation on each processor sum[Pn] = 0; for (i = 1000*Pn; i < 1000*(Pn+1); i = i + 1) sum[Pn] = sum[Pn] + A[i]; Now need to add these partial sums –Reduction: divide and conquer –Half the processors add pairs, then quarter, … –Need to synchronize between reduction steps

Modified by S. J. Fritz Spring 2009 (20) Chapter 7 — Multicores, Multiprocessors, and Clusters — 20 Example: Sum Reduction half = 100; repeat synch(); if (half%2 != 0 && Pn == 0) sum[0] = sum[0] + sum[half-1]; /* Conditional sum needed when half is odd; Processor0 gets missing element */ half = half/2; /* dividing line on who sums */ if (Pn < half) sum[Pn] = sum[Pn] + sum[Pn+half]; until (half == 1);

Modified by S. J. Fritz Spring 2009 (21) Chapter 7 — Multicores, Multiprocessors, and Clusters — 21 Message Passing Alternative to shared address space Each processor has private physical address space Hardware sends/receives messages between processors §7.4 Clusters and Other Message-Passing Multiprocessors

Modified by S. J. Fritz Spring 2009 (22) Chapter 7 — Multicores, Multiprocessors, and Clusters — 22 Loosely Coupled Clusters Network of independent computers –Each has private memory and OS –Connected using I/O system E.g., Ethernet/switch, Internet Suitable for applications with independent tasks –Web servers, databases, simulations, … High availability, scalable, affordable Problems –Administration cost (prefer virtual machines) –Low interconnect bandwidth c.f. processor/memory bandwidth on an SMP

Message Passing Message passing –processors communicate by explicitly sending and receiving messages. Send message- a routine used by processor with private memories to pass message to another processor Receive message – routine to accept message form another processor. Modified by S. J. Fritz Spring 2009 (23)

Clusters Clusters- collections of computers connected via I/O over standard network switches to form a message passing multiprocessor. Most widespread example of message passing parallel computers Modified by S. J. Fritz Spring 2009 (24)

Cluster Disadvantages Cost of administering a cluster of n processors is about the same as that of n independent machines. The administration cost of a shared memory multiprocessor with n processors is about the same as a single machine Cluster usually use the I/O connection, which is slower than the memory interconnect A Cluster has n independent memories, and n copies of the OS Modified by S. J. Fritz Spring 2009 (25)

Modified by S. J. Fritz Spring 2009 (26) Chapter 7 — Multicores, Multiprocessors, and Clusters — 26 Sum Reduction (Again) Sum 100,000 on 100 processors First distribute 100 numbers to each –The do partial sums sum = 0; for (i = 0; i<1000; i = i + 1) sum = sum + AN[i]; Reduction –Half the processors send, other half receive and add –The quarter send, quarter receive and add, …

Modified by S. J. Fritz Spring 2009 (27) Chapter 7 — Multicores, Multiprocessors, and Clusters — 27 Sum Reduction (Again) Given send() and receive() operations limit = 100; half = 100;/* 100 processors */ repeat half = (half+1)/2; /* send vs. receive dividing line */ if (Pn >= half && Pn < limit) send(Pn - half, sum); if (Pn < (limit/2)) sum = sum + receive(); limit = half; /* upper limit of senders */ until (half == 1); /* exit with final sum */ –Send/receive also provide synchronization –Assumes send/receive take similar time to addition

Modified by S. J. Fritz Spring 2009 (28) Chapter 7 — Multicores, Multiprocessors, and Clusters — 28 Grid Computing Separate computers interconnected by long-haul networks –E.g., Internet connections –Work units farmed out, results sent back Can make use of idle time on PCs –E.g., World Community Grid, –BOINC,

Modified by S. J. Fritz Spring 2009 (29) Chapter 7 — Multicores, Multiprocessors, and Clusters — 29 Multithreading Performing multiple threads of execution in parallel –Replicate registers, PC, etc. –Fast switching between threads Fine-grain multithreading –Switch threads after each cycle –Interleave instruction execution –If one thread stalls, others are executed Coarse-grain multithreading –Only switch on long stall (e.g., L2-cache miss) –Simplifies hardware, but doesn’t hide short stalls (eg, data hazards) §7.5 Hardware Multithreading

Modified by S. J. Fritz Spring 2009 (30) Chapter 7 — Multicores, Multiprocessors, and Clusters — 30 Simultaneous Multithreading In multiple-issue dynamically scheduled processor –Schedule instructions from multiple threads –Instructions from independent threads execute when function units are available –Within threads, dependencies handled by scheduling and register renaming Example: Intel Pentium-4 HT –Two threads: duplicated registers, shared function units and caches

Modified by S. J. Fritz Spring 2009 (31) Chapter 7 — Multicores, Multiprocessors, and Clusters — 31 Multithreading Example

Modified by S. J. Fritz Spring 2009 (32) Chapter 7 — Multicores, Multiprocessors, and Clusters — 32 Future of Multithreading Will it survive? In what form? Power considerations  simplified microarchitectures –Simpler forms of multithreading Tolerating cache-miss latency –Thread switch may be most effective Multiple simple cores might share resources more effectively

Multicore Processors Modified by S. J. Fritz Spring 2009 (33) Intel core i7 940 Quad Core Processor Hyperthreading- Intel’s name for simultaneous multithreading

Modified by S. J. Fritz Spring 2009 (34) Chapter 7 — Multicores, Multiprocessors, and Clusters — 34 Instruction and Data Streams An alternate classification §7.6 SISD, MIMD, SIMD, SPMD, and Vector Data Streams SingleMultiple Instruction Streams SingleSISD: Intel Pentium 4 SIMD: SSE instructions of x86 MultipleMISD: No examples today MIMD: Intel Xeon e5345 SPMD: Single Program Multiple Data A parallel program on a MIMD computer Conditional code for different processors

Instruction Streams SISD – Single Instruction stream, Single Data stream – a uniprocessor MIMD- Multiple Instruction stream, Multiple Data stream – a multiprocessor SIMD – Single instruction stream, multiple data streams – a multiprocessor, where the same instruction is applied to many data streams as in a vector or array processor. Modified by S. J. Fritz Spring 2009 (35)

SIMD Operate elementwise on vectors of data –E.g., MMX and SSE instructions in x86 Multiple data elements in 128-bit wide registers All processors execute the same instruction at the same time –Each with different data address, etc. Simplifies synchronization Reduced instruction control hardware Works best for highly data-parallel applications Modified by S. J. Fritz Spring 2009 (36) Chapter 7 — Multicores, Multiprocessors, and Clusters — 36

Modified by S. J. Fritz Spring 2009 (37) Chapter 7 — Multicores, Multiprocessors, and Clusters — 37 Vector Processors Highly pipelined function units Stream data from/to vector registers to units –Data collected from memory into registers –Results stored from registers to memory Example: Vector extension to MIPS –32 × 64-element registers (64-bit elements) –Vector instructions lv, sv : load/store vector addv.d : add vectors of double addvs.d : add scalar to each element of vector of double Significantly reduces instruction-fetch bandwidth

Modified by S. J. Fritz Spring 2009 (38) Chapter 7 — Multicores, Multiprocessors, and Clusters — 38 Example: DAXPY (Y = a × X + Y) Conventional MIPS code l.d $f0,a($sp) ;load scalar a addiu r4,$s0,#512 ;upper bound of what to load loop: l.d $f2,0($s0) ;load x(i) mul.d $f2,$f2,$f0 ;a × x(i) l.d $f4,0($s1) ;load y(i) add.d $f4,$f4,$f2 ;a × x(i) + y(i) s.d $f4,0($s1) ;store into y(i) addiu $s0,$s0,#8 ;increment index to x addiu $s1,$s1,#8 ;increment index to y subu $t0,r4,$s0 ;compute bound bne $t0,$zero,loop ;check if done Vector MIPS code l.d $f0,a($sp) ;load scalar a lv $v1,0($s0) ;load vector x mulvs.d $v2,$v1,$f0 ;vector-scalar multiply lv $v3,0($s1) ;load vector y addv.d $v4,$v2,$v3 ;add y to product sv $v4,0($s1) ;store the result

Modified by S. J. Fritz Spring 2009 (39) Chapter 7 — Multicores, Multiprocessors, and Clusters — 39 Vector vs. Scalar Vector architectures and compilers –Simplify data-parallel programming –Explicit statement of absence of loop-carried dependences Reduced checking in hardware –Regular access patterns benefit from interleaved and burst memory –Avoid control hazards by avoiding loops More general than ad-hoc media extensions (such as MMX, SSE) –Better match with compiler technology

Modified by S. J. Fritz Spring 2009 (40) Chapter 7 — Multicores, Multiprocessors, and Clusters — 40 History of GPUs Early video cards –Frame buffer memory with address generation for video output 3D graphics processing –Originally high-end computers (e.g., SGI) –Moore’s Law  lower cost, higher density –3D graphics cards for PCs and game consoles Graphics Processing Units –Processors oriented to 3D graphics tasks –Vertex/pixel processing, shading, texture mapping, rasterization §7.7 Introduction to Graphics Processing Units

Modified by S. J. Fritz Spring 2009 (41) Chapter 7 — Multicores, Multiprocessors, and Clusters — 41 Graphics in the System

Modified by S. J. Fritz Spring 2009 (42) Chapter 7 — Multicores, Multiprocessors, and Clusters — 42 GPU Architectures Processing is highly data-parallel –GPUs are highly multithreaded –Use thread switching to hide memory latency Less reliance on multi-level caches –Graphics memory is wide and high-bandwidth Trend toward general purpose GPUs –Heterogeneous CPU/GPU systems –CPU for sequential code, GPU for parallel code Programming languages/APIs –DirectX, OpenGL –C for Graphics (Cg), High Level Shader Language (HLSL) –Compute Unified Device Architecture (CUDA)

Modified by S. J. Fritz Spring 2009 (43) Chapter 7 — Multicores, Multiprocessors, and Clusters — 43 Example: NVIDIA Tesla Streaming multiprocessor 8 × Streaming processors

Modified by S. J. Fritz Spring 2009 (44) Chapter 7 — Multicores, Multiprocessors, and Clusters — 44 Example: NVIDIA Tesla Streaming Processors –Single-precision FP and integer units –Each SP is fine-grained multithreaded Warp: group of 32 threads –Executed in parallel, SIMD style 8 SPs × 4 clock cycles –Hardware contexts for 24 warps Registers, PCs, …

Modified by S. J. Fritz Spring 2009 (45) Chapter 7 — Multicores, Multiprocessors, and Clusters — 45 Classifying GPUs Don’t fit nicely into SIMD/MIMD model –Conditional execution in a thread allows an illusion of MIMD But with performance degredation Need to write general purpose code with care Static: Discovered at Compile Time Dynamic: Discovered at Runtime Instruction-Level Parallelism VLIWSuperscalar Data-Level Parallelism SIMD or VectorTesla Multiprocessor

Modified by S. J. Fritz Spring 2009 (46) Chapter 7 — Multicores, Multiprocessors, and Clusters — 46 Interconnection Networks Network topologies –Arrangements of processors, switches, and links §7.8 Introduction to Multiprocessor Network Topologies BusRing 2D Mesh N-cube (N = 3) Fully connected

Modified by S. J. Fritz Spring 2009 (47) Chapter 7 — Multicores, Multiprocessors, and Clusters — 47 Multistage Networks

Modified by S. J. Fritz Spring 2009 (48) Chapter 7 — Multicores, Multiprocessors, and Clusters — 48 Network Characteristics Performance –Latency per message (unloaded network) –Throughput Link bandwidth Total network bandwidth Bisection bandwidth –Congestion delays (depending on traffic) Cost Power Routability in silicon

Modified by S. J. Fritz Spring 2009 (49) Chapter 7 — Multicores, Multiprocessors, and Clusters — 49 Parallel Benchmarks Linpack: matrix linear algebra SPECrate: parallel run of SPEC CPU programs –Job-level parallelism SPLASH: Stanford Parallel Applications for Shared Memory –Mix of kernels and applications, strong scaling NAS (NASA Advanced Supercomputing) suite –computational fluid dynamics kernels PARSEC (Princeton Application Repository for Shared Memory Computers) suite –Multithreaded applications using Pthreads and OpenMP §7.9 Multiprocessor Benchmarks

Modified by S. J. Fritz Spring 2009 (50) Chapter 7 — Multicores, Multiprocessors, and Clusters — 50 Code or Applications? Traditional benchmarks –Fixed code and data sets Parallel programming is evolving –Should algorithms, programming languages, and tools be part of the system? –Compare systems, provided they implement a given application –E.g., Linpack, Berkeley Design Patterns Would foster innovation in approaches to parallelism

Modified by S. J. Fritz Spring 2009 (51) Chapter 7 — Multicores, Multiprocessors, and Clusters — 51 Modeling Performance Assume performance metric of interest is achievable GFLOPs/sec –Measured using computational kernels from Berkeley Design Patterns Arithmetic intensity of a kernel –FLOPs per byte of memory accessed For a given computer, determine –Peak GFLOPS (from data sheet) –Peak memory bytes/sec (using Stream benchmark) §7.10 Roofline: A Simple Performance Model

Modified by S. J. Fritz Spring 2009 (52) Chapter 7 — Multicores, Multiprocessors, and Clusters — 52 Roofline Diagram Attainable GPLOPs/sec = Max ( Peak Memory BW × Arithmetic Intensity, Peak FP Performance )

Modified by S. J. Fritz Spring 2009 (53) Chapter 7 — Multicores, Multiprocessors, and Clusters — 53 Comparing Systems Example: Opteron X2 vs. Opteron X4 –2-core vs. 4-core, 2× FP performance/core, 2.2GHz vs. 2.3GHz –Same memory system To get higher performance on X4 than X2 Need high arithmetic intensity Or working set must fit in X4’s 2MB L-3 cache

Modified by S. J. Fritz Spring 2009 (54) Chapter 7 — Multicores, Multiprocessors, and Clusters — 54 Optimizing Performance Optimize FP performance –Balance adds & multiplies –Improve superscalar ILP and use of SIMD instructions Optimize memory usage –Software prefetch Avoid load stalls –Memory affinity Avoid non-local data accesses

Modified by S. J. Fritz Spring 2009 (55) Chapter 7 — Multicores, Multiprocessors, and Clusters — 55 Optimizing Performance Choice of optimization depends on arithmetic intensity of code Arithmetic intensity is not always fixed May scale with problem size Caching reduces memory accesses Increases arithmetic intensity

Modified by S. J. Fritz Spring 2009 (56) Chapter 7 — Multicores, Multiprocessors, and Clusters — 56 Four Example Systems §7.11 Real Stuff: Benchmarking Four Multicores … 2 × quad-core Intel Xeon e5345 (Clovertown) 2 × quad-core AMD Opteron X (Barcelona)

Modified by S. J. Fritz Spring 2009 (57) Chapter 7 — Multicores, Multiprocessors, and Clusters — 57 Four Example Systems 2 × oct-core IBM Cell QS20 2 × oct-core Sun UltraSPARC T (Niagara 2)

Modified by S. J. Fritz Spring 2009 (58) Chapter 7 — Multicores, Multiprocessors, and Clusters — 58 And Their Rooflines Kernels –SpMV (left) –LBHMD (right) Some optimizations change arithmetic intensity x86 systems have higher peak GFLOPs –But harder to achieve, given memory bandwidth

Modified by S. J. Fritz Spring 2009 (59) Chapter 7 — Multicores, Multiprocessors, and Clusters — 59 Performance on SpMV Sparse matrix/vector multiply –Irregular memory accesses, memory bound Arithmetic intensity –0.166 before memory optimization, 0.25 after Xeon vs. Opteron Similar peak FLOPS Xeon limited by shared FSBs and chipset UltraSPARC/Cell vs. x86 20 – 30 vs. 75 peak GFLOPs More cores and memory bandwidth

Modified by S. J. Fritz Spring 2009 (60) Chapter 7 — Multicores, Multiprocessors, and Clusters — 60 Performance on LBMHD Fluid dynamics: structured grid over time steps –Each point: 75 FP read/write, 1300 FP ops Arithmetic intensity –0.70 before optimization, 1.07 after Opteron vs. UltraSPARC More powerful cores, not limited by memory bandwidth Xeon vs. others Still suffers from memory bottlenecks

Modified by S. J. Fritz Spring 2009 (61) Chapter 7 — Multicores, Multiprocessors, and Clusters — 61 Achieving Performance Compare naïve vs. optimized code –If naïve code performs well, it’s easier to write high performance code for the system SystemKernelNaïve GFLOPs/sec Optimized GFLOPs/sec Naïve as % of optimized Intel XeonSpMV LBMHD % 82% AMD Opteron X4 SpMV LBMHD % 50% Sun UltraSPARC T2 SpMV LBMHD % 93% IBM Cell QS20SpMV LBMHD Naïve code not feasible %

Modified by S. J. Fritz Spring 2009 (62) Chapter 7 — Multicores, Multiprocessors, and Clusters — 62 Fallacies Amdahl’s Law doesn’t apply to parallel computers –Since we can achieve linear speedup –But only on applications with weak scaling Peak performance tracks observed performance –Marketers like this approach! –But compare Xeon with others in example –Need to be aware of bottlenecks §7.12 Fallacies and Pitfalls

Modified by S. J. Fritz Spring 2009 (63) Chapter 7 — Multicores, Multiprocessors, and Clusters — 63 Pitfalls Not developing the software to take account of a multiprocessor architecture –Example: using a single lock for a shared composite resource Serializes accesses, even if they could be done in parallel Use finer-granularity locking

Modified by S. J. Fritz Spring 2009 (64) Chapter 7 — Multicores, Multiprocessors, and Clusters — 64 Concluding Remarks Goal: higher performance by using multiple processors Difficulties –Developing parallel software –Devising appropriate architectures Many reasons for optimism –Changing software and application environment –Chip-level multiprocessors with lower latency, higher bandwidth interconnect An ongoing challenge for computer architects! §7.13 Concluding Remarks