Characterization of Monolithic Flip Chip Column Grid Array Packaging with Underfill (New) Description:FY08 Plans: Schedule/Costs: NASA and Non-NASA Organizations/Procurements: Deliverables: The trend in the EEE parts manufacturing industry is to increase the size and functions of monolithic chips, thus pushing the envelope of packaging. Existing packaging of electronic parts has reached the point where conventional methods can no longer accommodate the number of leads. Field Programmable Gate Arrays (FPGAs), for one, are experiencing a new experimental packaging technology using flip chip technology with column grid arrays with underfill bonding to the flip chip. Before using this type of packaging technology in space applications, extensive characterization of is needed to better understand the risks involved in using this technology. Since this type of packaging is so large that it does not lend itself to a hermetic seal, this poses problems to the NASA Human Space Flight community. DSCC QMLV certification may not be achievable because of the lack of a hermetic seal. Evaluation of the effectiveness of the packaging technique to seal out moisture needs to be performed. Tensional stresses and reaction to space environments need to be evaluated for the underfill technology. Quality and integrity of the leads need to be verified. Lead Center/PI: GSFC, Dr. Lois Scaglione Item #1 deliverable would be trip reports (white paper) containing a detailed description of the DSCC certification process issues. Item #2 deliverable would be the accelerated hermetic seal experiment, test results and analysis of failures in a detailed report. Recommendations for qualification of the part packaging will be made. Since Xilinx FPGAs are already using this technology, two of these parts would be procured, in a ‘daisy chain’ configuration. Two parts would be tested for hermetic seal effectiveness in an 100 cycle accelerated test at ranges of very low to very high temperatures. The parts would then be opened to verify that no corrosion effects have taken place. Laboratory tests, such as SEM would document corrosion if it exists. The effect on the Underfill would also be characterized and documented. These same parts would initially be used to evaluate the quality of the bonding leads, including integrity and conductive consistency. Various techniques, such as X-ray, would be used to determine the most effective way to evaluate the manufacturing quality of the external leads. A NASA representative would work with DSCC on the certification of the part packaging and be part of the certification team at the IBM plant in Bromont, Canada. Parts will be purchased from Xilinx and testing will be done to the fullest extent at GSFC with support from the GSFC contractor personnel. Some testing suggestions may be made to IBM Bromont and Xilinx when beyond the scope of GSFC laboratories with an analysis of results at GSFC. Characterization of Monolithic Flip Chip Column Grid Array Packaging with Underfill FY 2010 Procure Xilinx parts Visit Bromont Characterize parts Write reports