Daniel Belver VIII Workshop on RPC and Related Detectors, Seoul October 10th 2005 The Front End Electronics for the HADES RPC wall (ESTRELA-FEE) Daniel Belver - University of Santiago de Compostela, Spain labCAF

Daniel Belver VIII Workshop on RPC and Related Detectors, Seoul October 10th 2005 OUTLINE HADES Introduction. A RPC cell. The ESTRELA FEE. First STEPS. STEP3. Measurements: time jitter, crosstalk and Q-ToT behaviour. STEP4. Comments. Summary.

Daniel Belver VIII Workshop on RPC and Related Detectors, Seoul October 10th 2005 HADES High Acceptance Di-Electron Spectrometer HADES (GSI, Darmstadt) is an experiment devoted to study the properties of the nuclear matter in pp and NN collisions at kinetic energies from 1-2 GeV/A. HADES back view RPC HADES side view Beam

Daniel Belver VIII Workshop on RPC and Related Detectors, Seoul October 10th 2005 Main Requirements: - Time resolution below 100 ps. - Working rate: ~600 Hz/cm 2. - Charge measurement for calibration purposes. - Crosstalk as small as possible. RPC WALL GOAL RPC WALL GOAL For high multiplicity experiments HADES needs a detector covering the small angle region of the spectrometer for low level triggers and electron identification purposes: TRIGGER 1: Multiplicity trigger. TRIGGER 2: Lepton detection.

Daniel Belver VIII Workshop on RPC and Related Detectors, Seoul October 10th 2005 Side view of some cells A RPC cell RPC cell used in April03 tests in HADES 4 gap RPC New design for Nov05 tests in HADES: 2 layers Some cells in one sector 48 cells of the expected 320/sector

Daniel Belver VIII Workshop on RPC and Related Detectors, Seoul October 10th 2005 GSI-HADES, April 03 TEST UPSTREAM VIEW SCINTILLATORS FOR TRIGGER RPC C beam, 1GeV/A

Daniel Belver VIII Workshop on RPC and Related Detectors, Seoul October 10th 2005 TIME-CHARGE MEASUREMENTS Before ‘slewing correction’After ‘slewing correction’ t [ps] t [ps]

Daniel Belver VIII Workshop on RPC and Related Detectors, Seoul October 10th 2005 Geometric inefficiency ~15 % RESULTS Electric crosstalk between cells below 0.4% No degradation observed for multiple hits in neighbouring cells

Daniel Belver VIII Workshop on RPC and Related Detectors, Seoul October 10th 2005 The ESTRELA FEE STEP0: A. Blanco, P. Fonte et al (IEEE Trans. Nucl. Sci. 48(2001)n4, 1249). - 1 channel in 2 boards. TTL + NIM output. ADC output. - No longer available components. STEP1: Available components. - 1channel / 2-layers board. - ECL digital output. ADC output. - A dead time window of 1μs is implemented to avoid retriggering of the comparator. STEP2: Tested in our laboratories. - 2channels / 4-layers board. - The charge is determined through a measurement of the Time Over Threshold (ToT). - LVDS output.

Daniel Belver VIII Workshop on RPC and Related Detectors, Seoul October 10th 2005 The ESTRELA FEE STEP3: Tested in our laboratories. - Daughterboard (DB) + Motherboard (MB). - DB:4 channels / 6-layers board + MB: 32 channels / 8-layers board. - 2 amplifying stages: PHILIPS BGA-2712 (21dB, 1GHz) + GALI-S66 (18dB, 2GHz). - LVDS output: its width gives us the ToT, proportionally to RPC charge. - Time Over Threshold (ToT) charge measurement implemented too. - Latch enable of the comparator used to close the digital signal. STEP4: An update of STEP3 board. - Only one amplifier step, GALI-S66 (18dB, 2GHz).

Daniel Belver VIII Workshop on RPC and Related Detectors, Seoul October 10th 2005 The STEP3 board The STEP3 board MB DB Motherboard (MB) + Daughterboard (DB) philosophy. - MB (GSI: S. Lange): 32 channels / 8-layers board. Regulators, Threshold DACs, Test pulses, Trigger logic. - DB (CIEMAT, USC): 4 channels / 6-layer board (50x45mm 2 =22.5cm 2 ). 2 amplification stages, digitization (LVDS out). Q-ToT implemented, latch enable input comparator is used. DB’s MB’s

Daniel Belver VIII Workshop on RPC and Related Detectors, Seoul October 10th 2005 One-channel DB logic - Amplifier stage (analog stage): - PHILIPS BGA GALI-S66. - Q-ToT stage with TI OPA Digital stage: - Dual MAXIM9601 comparator. Latch enable input used for cut and shape the output pulse. - PECL-LVDS PHILIPS PTN3311 converter. - PHILIPS BFT92 transistor for multiplicity trigger sum. 4 ch. out C C ToT Integrator Amplifiers PECL- LVDS ToF-Threshold ToT-Threshold In OPA690 Wideband Op. Amplifier BGA2712 MMIC Wideband (21dB 1GHz) GALI-S66 Monolithic (18dB 2GHz) MAX9601-2ch 500ps Propagation Delay PTN3311 C Latch enable MAX9601-2ch R 2k2Trigger Out. Σ 4ch. SAMTEC 16 diff. pins BFT92 Wideband PNP Transistor

Daniel Belver VIII Workshop on RPC and Related Detectors, Seoul October 10th 2005 Latch Enable configuration Latch Enable is used like another comparator working when two digital levels cross through. MAXIM Comparator Latch Enable TOT Comparator OUT TOF Comparator OUT

Daniel Belver VIII Workshop on RPC and Related Detectors, Seoul October 10th 2005 Laboratory tests We have performed the following tests: 1) Time resolution of the FEE electronics (jitter). 2) Crosstalk between channels. 3) Charge / Time Over Threshold correlation (Q-ToT). The FEE board have been tested in our laboratory with an 600 MHz Agilent 81130A pulser and with a prototype ESTRELA cell.

Daniel Belver VIII Workshop on RPC and Related Detectors, Seoul October 10th 2005 Jitter measurements With a 600MHz pulser.

Daniel Belver VIII Workshop on RPC and Related Detectors, Seoul October 10th 2005 Jitter measurements With RPC signals (studying the time difference between the two RPC sides) 1. Ilumination with a gamma source from a side, the smoothening of the edge of the detector provides an estimate of the electronic jitter. 2.Illumination with a gamma source in coincidence with a reference scintillator to guarantee point-like illumination. The width of the time difference is the electronic jitter. 30ps ≤ Time jitter ≤ 45ps

Daniel Belver VIII Workshop on RPC and Related Detectors, Seoul October 10th 2005 Crosstalk measurements Crosstalk effects in all channels of the same board and in different DBs have been studied. We measured the ratio of signals in a channel not connected to the RPC induced by its neighbour channel connected to the RPC. Crosstalk in all channels less than 1%. No effects observed in the time jitter due to possible fluctuations of the base line.

Daniel Belver VIII Workshop on RPC and Related Detectors, Seoul October 10th 2005 Q-ToT Behaviour Behaviour with RPC signals seems good. Further tests are needed regarding stability. Analog signal Integrated signal Output LVDS signal TOT Threshold C1C1 R3R3 R2R2 R1R1

Daniel Belver VIII Workshop on RPC and Related Detectors, Seoul October 10th 2005 The STEP4 board Amplifier stage (analog stage): - GALI-S66. - Q-ToT stage with TI OPA690. Digital stage: - Dual MAXIM9601 comparator. Latch enable input used for cut and shape the output pulse. - PECL-LVDS Texas Ins. SN65LVDT100 converter. - BFT92 transistor for multiplicity trigger sum. 4 ch. out C C ToT Integrator Amplifier Step PECL- LVDS ToF-Threshold ToT-Threshold In OPA690 Wideband Op. Amplifier GALI-S66 Monolithic (18dB, 2GHz) MAX9601-2ch 500ps Propagation Delay SN65LVDT100 C Latch enable MAX9601-2ch R 2k2Trigger Out. Σ 4ch. SAMTEC 16 diff. pins BFT92 Wideband PNP Transistor

Daniel Belver VIII Workshop on RPC and Related Detectors, Seoul October 10th STEP3 features: - Motherboard-Daughterboard arrangement. - 8 Daughterboards / Motherboard. - 4ch / 6-layer Daughterboard of 22.5 cm 2 (1.2W/channel). - Electronics Time Jitter below 40ps. - Q-ToT method implemented. - STEP4 features: - The same philosophy that STEP3. - One amplifier step: only GALI-S66 (18dB, 2GHz). - Next steps: Nov 05: Test on beam at GSI with a 24 cells prototype (48 FEE channels). SUMMARY

Daniel Belver VIII Workshop on RPC and Related Detectors, Seoul October 10th 2005

Time of Flight (ToF) We measured the ToF with the whole system: final RPC cells, MB and 3 DB with 12 channels connected. We measured the time difference between 2 channels, using a scintillator.

Daniel Belver VIII Workshop on RPC and Related Detectors, Seoul October 10th 2005 FEE STEP2 board: One-channel logic reset ToT Integrator ToT-Threshold C C Amplifiers D Flip-Flop Gate PECL- LVDS ToF-Threshold In Out Digital Passive Delay OPA655 Wideband Op. Amplifier (Delay=  s) BGA2712 MMIC Wideband (21dB 1GHz) MSA-0786 Silicon Bipolar MMIC (12.5dB 1GHz) MAX9601-2ch 500ps Propagation Delay MC100EL29-2ch Set/Reset MC10EL05 AND/NAND PTN3311 C MAX9601-2ch PECL-LVDS GATE DIGITAL DELAY FLIP-FLOP REGULATORS COMPARATOR INTEGRATOR PHILIPS AMPLIFIER AGILENT AMPLIFIER - 2 channels / 4-layers board (~24 cm 2 ). - ToT charge measurement implemented. - One LVDS output signal per channel: Time (leading edge) + Charge (pulse width). - Power consumption ≈ 2.5 W/channel (non optimized). - Three voltage regulators: +5 V, -5 V, +3.3 V.

Daniel Belver VIII Workshop on RPC and Related Detectors, Seoul October 10th 2005 Jitter Measurements With a 600MHz pulser. With a RPC cell (edge measurement): We illuminate the RPC cell in one of its sides with a 60 Co source. If non electronic time jitter were present, distribution of time differences measured at both edges would show a sharp cut indicating the end of the detector. Electronic jitter smoothens the cut and moves it into a Gaussian tail where the time jitter can be estimated. Cell edge

Daniel Belver VIII Workshop on RPC and Related Detectors, Seoul October 10th 2005 Crosstalk measurements Crosstalk effects in both channels of the same board have been studied. We measured the ratio of signals in a channel not connected to the RPC induced by its neighbour channel connected to the RPC. Crosstalk in front channel less than 0.5%. Crosstalk in rear channel compatible with 0%. No explanation for this asymmetry (design effect or accident?). No effects observed in the time jitter due to possible fluctuations of the base line.

Daniel Belver VIII Workshop on RPC and Related Detectors, Seoul October 10th 2005 Q-ToT Behaviour - Good linear behaviour observed with pulse generator. - Poor behaviour observed with real signals (+ some saturation at high Q). - Inaccurate charge selection (scope glitch trigger method). - Not shaping filters careful tuning still done. - Higher thresholds range needed (0-50mV shows to be to small). - But: - Good behaviour has been observed for most signals. - ’Difficult’ events: streamers, avalanches with high ionic tail. RPC prototype cellPulser

Daniel Belver VIII Workshop on RPC and Related Detectors, Seoul October 10th 2005 Charge Measurement Charge Q is measured loocking at the time the integrated signal is over a given threshold (Q/TOT method) Charge Q is measured loocking at the time the integrated signal is over a given threshold (Q/TOT method) Integrated signal Analog signal Digitized signal Threshold Width C1C1 R3R3 R2R2 R1R1 C2C2 R 1 C 1 : Integration time R 2 C 1 : Decreasing time R 3 C 2 : Overshoot time V TOT threshold tunable between 0 and -50mV

Daniel Belver VIII Workshop on RPC and Related Detectors, Seoul October 10th 2005