VLSI SP Course 2001 台大電機吳安宇 Multirate Processing of Digital Signals: Fundamentals For NTUEE VLSI Signal Processing Course Instructor: 吳安宇教授

VLSI SP Course 2001 台大電機吳安宇 Outline Introduction Sampling Rate Conversion Multistage Implementation Practice Structure Polyphase Implementation

VLSI SP Course 2001 台大電機吳安宇 Motivation Definition –More than one sampling rate (clock) are used in a system Module 1Module 2 clock 1 clock 2 ?

VLSI SP Course 2001 台大電機吳安宇 Conversion Approach Analog approach Digital approach (multirate DSP system)

VLSI SP Course 2001 台大電機吳安宇 Analog Approach Advantages Simple Straightforward Arbitrary sampling rate Disadvantages D/A & A/D converter are needed Ideal (near perfect) lowpass filter is needed Introduced noise and distortion

VLSI SP Course 2001 台大電機吳安宇 Digital Approach Sampling rate conversion –Interpolation Increase the sampling rate –Decimation Decrease the sampling rate

VLSI SP Course 2001 台大電機吳安宇 Sampling Theory If the highest frequency component in a signal is f max, then the signal should be sampled at the rate of at least 2f max for the samples to describe the signal completely, i.e., For F s < 2f max, alias occurs in the sampling process.  Alias Distortion (aliasing)

VLSI SP Course 2001 台大電機吳安宇 Aliasing f max FsFs f -F s X(f)

VLSI SP Course 2001 台大電機吳安宇 Interpolation by L LL h(m)h(m)

VLSI SP Course 2001 台大電機吳安宇 Interpolation by L LL h(m)h(m)

VLSI SP Course 2001 台大電機吳安宇 Decimation by M h(m)h(m) MM

VLSI SP Course 2001 台大電機吳安宇 h(m)h(m) MM Decimation by M

VLSI SP Course 2001 台大電機吳安宇 Conversion by a Rational Factor M/L Cascade of two process LL h1(m)h1(m)h2(m)h2(m) MM Interpolation by LDecimation by M

VLSI SP Course 2001 台大電機吳安宇 Conversion by a Rational Factor M/L A more efficiency implementation LL h (m)h (m) MM

VLSI SP Course 2001 台大電機吳安宇 Multistage Implementation LL h(m)h(m) L1L1 h(m)h(m) L2L2 LILI L1L1 h1(m)h1(m) L2L2 h2(m)h2(m) L1L1 h1(m)h1(m)

VLSI SP Course 2001 台大電機吳安宇 Multistage Implementation Advantages Reduce the complexity Reduce storage devices (registers) Simplify (relax) filter design problem Reduce the finite wordlength effect Disadvantages Increase the control circuit Difficulty in choosing I and best L j for 1  i  I

VLSI SP Course 2001 台大電機吳安宇 Interpolated FIR (IFIR) Approach Nothing to do with interpolation and decimation Conceptually similar Suitable for narrowband FIR filter design LPF HPF BPF

VLSI SP Course 2001 台大電機吳安宇 Desired narrowband response Assume required filter order is N. Stretched filter Required filter order is reduced to N/2. Interpolated version of stretched filter Required filter order is still N/2. DesiredUndesired Image suppresser Required filter order is M. Order (N/2+M) is needed to implement! (N/2+M) << N for small M Application: Interpolated FIR (IFIR)

VLSI SP Course 2001 台大電機吳安宇 Interpolated FIR (IFIR) (a) G(z)(a) G(z 2 ) (a) G(z 2 )I(z)(b) I(z)

VLSI SP Course 2001 台大電機吳安宇 Interpolated FIR (IFIR) Quantity Compared Filter order Number of Multipliers Number of Adders Conventional Method IFIR Method G(z)I(z)Total

VLSI SP Course 2001 台大電機吳安宇 Some Useful Operations Duality and Transposition A dual system is that performs a complementary operation to that of an original system, and it can be constructed form the original system through the process of transposition. The transposition operation is one in which the direction of all branches in the network are reversed, and the roles of the input and output of the network are interchanged.

VLSI SP Course 2001 台大電機吳安宇 Duality and Transposition transposition z -1

VLSI SP Course 2001 台大電機吳安宇 LL Duality and Transposition They are not true in time-varying system, but can be treated as sampling rate reverse process. LL  M M  M M  M M h(n)h(n)  M M h(n)h(n)  M M h(n)h(n) LL  M M h(n)h(n)  L L transposition

VLSI SP Course 2001 台大電機吳安宇 Practical Structure Decimation  M M h(n)h(n) z -1  M M  M M  M M  M M  M M  M M  M M  M M  M M

VLSI SP Course 2001 台大電機吳安宇 Practical Structure Interpolation LL h(n)h(n) z -1 LL LL LL LL LL LL

VLSI SP Course 2001 台大電機吳安宇 Application: Polyphase FIR Filter Polyphase decomposition h(n)h(n) z -1 E0(zM)E0(zM) E1(zM)E1(zM) E M-1 (z M )

VLSI SP Course 2001 台大電機吳安宇 Polyphase FIR Filter Noble identity E (zM)E (zM) MM E (z)E (z) MM E (z)E (z) LL E (zM)E (zM) LL

VLSI SP Course 2001 台大電機吳安宇 Polyphase FIR Filter H (z)H (z) 33 z -1 33 h0h0 h1h1 h2h2 h3h3 h4h4 h5h5 h0h0 z -3 33 h3h3 h1h1 h4h4 h2h2 h5h5 z -1 33 E0(z3)E0(z3) E1(z3)E1(z3) E2(z3)E2(z3)

VLSI SP Course 2001 台大電機吳安宇 Polyphase FIR Filter z -1 E0(z3)E0(z3) E1(z3)E1(z3) E2(z3)E2(z3) 33 33 33 h0h0 z -3 h3h3 h1h1 h4h4 h2h2 h5h5 z -1 33 33 33 E0(z)E0(z) E1(z)E1(z) E2(z)E2(z) 33 33 33 33 33 33 h0h0 h3h3 h1h1 h4h4 h2h2 h5h5

VLSI SP Course 2001 台大電機吳安宇 Structure Comparison z -1 33 33 33 h0h0 h3h3 h1h1 h4h4 h2h2 h5h5 33 33 33 33 33 33 h0h0 h1h1 h2h2 h3h3 h4h4 h5h5 Direct implementation Polyphase implementation