13 June 2006 R. Bonnefoy, C. Carloganu, E. Conte, R. Cornat, E. Delage, J. Lecoq, M.-L. Mercier, S. Monteil, P. Perret LPC Clermont PS Front-End Electronics.

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Presentation transcript:

13 June 2006 R. Bonnefoy, C. Carloganu, E. Conte, R. Cornat, E. Delage, J. Lecoq, M.-L. Mercier, S. Monteil, P. Perret LPC Clermont PS Front-End Electronics Production & Tests

Production Same strategy than the LAL’s one adopted for fabrication and tests:  2 prototypes  A pre-series: 1 full crate i.e. 14 boards  Series production: 3x 2x16

Tests at Production Site  Production flow:  All the PCBs and components are checked upon reception at the factory  Visual controls of the boards  Takaya tests (flying probes)  Partial boundary scan (JTAG) with an external chain:  8 AX  3 APA

Tests at Production Site (cont)  Power consumption measurements and aging tests 8 cycles of 9 hours:  Groups of 16 powered boards in a same crate

Tests at Lab’  Functional Tests:  Same (systematical) tests than for proto repeated:  I2C communications test (ECS)  Pedestals stability and noise  Digitization (ADC) by analog signal injection  FE-PGA with RAM pattern injection tests  DAQ path: FE-PGA / SEQ-PGA / CROC  Synchronisation and delay chips  Clock & reset to VFE  TRIG-PGA with RAM pattern injection tests:  Search for neighbour  SPD multiplicity  TRIGGER path: communications (PS/SPD/ECAL/VALIDATION/SPD MULT)

Tests of the communication 8 FEPGA SEQ ECAL1 FE PS BCID (5b), val1 (5b), val2 (8b) ECAL1 BCID (5b), energy(8b) ECAL2 BCID (5b), energy(8b) PS trig (64b) SPD trig (64b) Multiplicity (7b) PS BCID(8b) spare (6b) SPD trig (64b) PS data (8*8*10b) L0 data (8*20b) PS Right(8b), SPD Right(8b), spare(4b) PS corner (1b), SPD corner (1b) PS Bottom(8b), SPD Bottom (8b), spare (3b) FE BOARD ECAL2 FE SPD VFE PS VFE PS FE Board LEFT PS FE Board BOTTOM CROC SPD Control Board Validation card L0 data Croc (21b) TRIG PS Right (8b), SPD Right (8b), spare (4b), PS corner (1b), SPD corner (1b) PS FE Board TOP PS FE Board RIGHT  A lot !!! MEM CARD 1 BOTTOM NEIGHBOUR, VALIDATION CARD MEM CARD 2 LEFT NEIGHBOUR, SPD VALIDATION MEM CARD 3 NEIGHBOUR EMULATION MEM CARD 5 ECAL EMULATION MEM CARD 4 SPD EMULATION

Test bench

Wave forms generator Clock generator & fan-out Analogue fan-out Digital patterns RAMS AX1000 GLUE SEQ Test bench (cont’)

Conclusion  We are almost ready to start the production:  Few tests to be completed (VFE, mapping, …)  FE-PGA programming to be launched  Price inquiry finished  Visit and selection of the manufacturer: within 2 weeks  Proto fabrication could start beginning of July  Automation of the lab test procedure

–Program (APA) –Test (externally cabled JTAG chain thanks to individual connectors) JTAG TESTS