The Clock Distribution inside the CTA Camera Axel Kretzschmann, DESY Zeuthen,

Features will distribute a clock and a synchronous data- line for date, timestamp etc. up to 500 MHz (400 MHz for Altera interface) interface to external clock source outputs not individual tunable (in this version) transmission : LVDS via CAT6A cable maximal 576 cluster (a 7 pix = 4032 pixel) optional: trigger broadcasting one standard crate, 6U high PCB form factor: Doppel-Euro

ClockData Control Basic Scheme function: providing a clock and timestamp synchronous to all Front-End-Modules interface to external source of clock and data, e.g. MUTIN card

ClockData Control Basic Scheme function: providing a clock and timestamp synchronous to all Front-End-Modules interface to external source of clock and data, e.g. MUTIN card

ClockData Control 1 to 24 Fanout Module main aim of design: low jitter concept: 2 stages of fanouts only a single type of PCB is needed basic scheme of the 1-to-24-Fanout-Module

cascading the basic modules in 2 levels gives max 576 clock lines = 4032 pixel

interface to external source of clock and data, e.g. MUTIN card function: providing a clock synchronous to all Front-End-Modules

optional function: a) collecting a signal from all trigger boards and broadcast this to all Front-End-Modules b) broadcast other information OR

test version of 1 to 24 Fanout Module 1 channel 1=>12

testing performance: maximum frequency => good enough cascaded 2 stages: works up to 900 MHz cascaded 5 stages: works up to 600 MHz BW oszi: 800 MHz

test setup

Overview Jitter Performance of the Clock Distribution Chain ADCLK854 Broadband Random Jitter: typ 150 fs rms ADCLK854 Broadband Random Jitter: typ 150 fs rms Clock Source LVDS Receiver with PLL 2 m cable adds crosstalk induced jitter: ??? ps internal Broadband Random Jitter: 1,3 ps peak-peak => ok => good enough

Overview Skew Performance of the Clock Distribution Chain ADCLK854 Output Skew: max 65 ps On the Same Part ADCLK854 Output Skew: max 390 ps Across Multiple Parts Clock Source LVDS Receiver with PLL 0,5 m cable: ps skew 2 m cable: ps skew sum: max +- 1,0 ns skew => good enough or inadequate ??

discussion skew estimated cable skew: % of traveling time 1 m = 4,2 ns=> at 0,5 m: ps => at 2 m: ps performance given by factory: Draka Light Blue: impedance: Ohm SCP solid:impedance: Ohm ELBROimpedance: Ohm, propagation delay skew 0,2 ns / 1 m Lappkabelimpedance: Ohm ortronicsimpedance: Ohm additional: skew = f( temperature, voltage, age)

timing performance over all components of the camera front endclock distribution system trigger board skew < 1,0 ns PM delay time skew < 5 ns accumulated skew < 1 ns time should be made isochronous at this layer

ClockData Control interface to external source of clock and data, e.g. MUTIN card features: will distribute a clock and a synchronous data-line for date, timestamp etc. up to 500 MHz (400 MHz Altera) interface to external clock source outputs not individual tunable (in this version) transmission : LVDS via CAT6A cable maximal 576 cluster (a 7 pix = 4032 pixel) optional: trigger broadcasting clock distribution system

how to cure to much skew: 1. measure sets of similar cables: lose cost and easy spare parts providing 2. buy sets of similar cables: lose cost and easy spare parts providing 3. use tunable fan-out-drivers:lose jitter, cost, adjustment procedure 4. make cables shorter:leads to complex design of camera 5. use better cables:lose cost 6. use glass-fibrelose cost, complex handling 7. invent a smart method with use of the existing camera hardware to make sure that skew is better than lower limit and automatically find bad skew cables: a challenge, depends on camera hardware 8. the camera hardware has to work with this clock conditions

RJ45 2x6 fold RJ45 2x6 fold RJ45 Cyclone 4 big or small version supply con. interfaceDC/DC 3 col LED RS232 3 col LED -supply: 12 V -SPI Bus 24 jacks LVDS output Block Diagram of the 1 to 24 Fanout Module supply con.

RJ45 2x6 fold RJ45 reset ic 3 col LED Block Diagram of V1 RJ45 oszill.

1 to 24 Fanout Module as Crate Master GPS Module Master- of- Camera- PC front panel 12 V SPI Bus

1 to 24 Fanout Module as stage-2-fanout 24 cables to Front- End front panel 12 V SPI Bus

19 inch crate front-side-only gives 13 x 24 = 312 cluster (= 2184 pixel) 1897 pixel needs 12 modules, => one slot free for…. 6 units = 260mm 6 TE = 30mm

two 19 inch crates front-side-only gives (13+11) x 24 = 576 cluster (= 4032 pixel)