M.N Minard Trigger Validation Board Tests and Implantation Cyril Drancourt, Pierre-Yves David,Victor Coco, Thomas Chouvion,M.N Minard - Production status & static tests - Dynamic Tests - Foreseen schedule

M.N Minard Production status -35 Boards produced (30 arrived in May ) - Tested at the soldering firm (X-rays – optical tests) -Passive and active componetns tested All OK - 8 at the pit – 27 in Annecy -Jtag test _ test 95% bga’s connexions 34 OK - 1 FPGA is being changed(18/07) - Mezzanine cards - 8 at pit - 25 in Annecy on TVB. 1 card has been repared broken component

M.N Minard Dynamic tests - Automatic process to determine sampling front & delay chip & fifo - read register – Input & output Spy Memories - Scan the delay-chip phase : test delay chip behaviour - Test the front setting - Test the data sampling in a global way - Test the FPGA treatment - In HCAL & EPPI FPGA - Test test sequence : -Scan delay chip rising and falling front (Sequential & Random) -Adjust Delay chip -Data time alignement : adjust Fifo -For the choosen setting - test FPGA treatment for HCAL& EPPI (sequential Pattern) -

M.N Minard Dynamic tests - Setup - 8 XCAL board - Croc V2 - PSSPD & HCAL from ECAL - TVB - Firmware = V3 for all and tests with V4(3) -Not always the same results in V3/V cards tested All channels responding for 24 cards On 1 card no response from ECAL EPPI -

M.N Minard Delay Chip range determination -

M.N Minard Delay chip range determination ns

M.N Minard Delay Chip range determination - HCAL FPGA - In average 2x 8 values possible - 2 cards with smaller range - several processing done : results stable - reload FPGA program : problem disappear ? -EPPI FPGA - In average 3.5 x 2 values possible - Problem stable with processing - Study the channel dependencies

M.N Minard EPPI range determination - The constraint comes from ECAL part Delay range authorized/ ns Channel 3 Channel 1 Channel 5 Difference (ns) beginning authorized zone /Channel 1 Channel 5 Channel 3

M.N Minard Test of the FPGA treatment - -Method -Calculate from spy input the expected output candidate & compare -Done with random LUT -With a pattern test - Test on 24 FPGA - Test HCAL fails 2 times -A shift of 1 level on 2 of the 4 output - No matching in any channel ( in debug) - Test EPPI - Fails once ( to be debugged) -Test with random pattern & other LUT configurations - In Progress

M.N Minard Planning -Next week do the test with V4 for all FPGA & study the individual channel to give info to Cyril - Work on firmware August ( Cyril ) -Fixe small mismatchs -Improve the EPPI range - Redo the tests for all the cards ( end-august ) with new version ? - Mezzanine test ( august) -The actual setup allows tell1 to read buffer !!! We do not succeeded to reload FPGA when the mezzanine card was there (to be understood) - Install all cards in September