SYEN 3330 Digital SystemsJung H. Kim Chapter 3 1 SYEN 3330 Digital Systems Chapter 3.

Slides:



Advertisements
Similar presentations
Documentation Standards
Advertisements

Combinational Circuits CS370 – Spring BCD to 7 Segment Display Controller Understanding the problem: input is a 4 bit bcd digit output is the control.
COE 202: Digital Logic Design Combinational Circuits Part 1
SYEN 3330 Digital SystemsJung H. Kim Chapter SYEN 3330 Digital Systems Chapters 4 – Part3: Verilog – Part 1.
Multiplexors Sequential Circuits and Finite State Machines Prof. Sin-Min Lee Department of Computer Science.
SYEN 3330 Digital SystemsJung H. Kim 1 SYEN 3330 Digital Systems Chapter 6 – Part 1.
SYEN 3330 Digital SystemsJung H. Kim Chapter5-1 1 SYEN 3330 Digital Systems Chapter 5 – Part 1.
Combinational Logic Design
1 Homework Reading –Tokheim, Section 5-10, 7-4 Machine Projects –Continue on MP4 Labs –Continue labs with your assigned section.
SYEN 3330 Digital SystemsJung H. Kim Chapter SYEN 3330 Digital Systems Chapter 2 – Part 4.
SYEN 3330 Digital SystemsJung H. Kim Chapter SYEN 3330 Digital Systems Chapter 2 -Part 8.
SYEN 3330 Digital SystemsJung H. Kim Chapter SYEN 3330 Digital Systems Chapter 2 -Part 2.
SYEN 3330 Digital SystemsJung H. Kim Chapter SYEN 3330 Digital Systems Chapter 2 – Part 1.
Charles Kime & Thomas Kaminski © 2008 Pearson Education, Inc. (Hyperlinks are active in View Show mode) Chapter 3 – Combinational Logic Design Part 1 –
Chapter 4 Logic Gates and Boolean Algebra. Introduction Logic gates are the actual physical implementations of the logical operators. These gates form.
Combinational Logic1 DIGITAL LOGIC DESIGN by Dr. Fenghui Yao Tennessee State University Department of Computer Science Nashville, TN.
ENGIN112 L12: Circuit Analysis Procedure September 29, 2003 ENGIN 112 Intro to Electrical and Computer Engineering Lecture 12 Circuit Analysis Procedure.
SYEN 3330 Digital Systems Jung H. Kim Chapter SYEN 3330 Digital Systems Chapter 2 – Part 5.
Week 3- slide 1 EE 231 Digital Electronics Fall 01 Gate Logic: Two-Level Simplification K-Map Method Examples F = A asserted, unchanged B varies G = B’,
Charles Kime & Thomas Kaminski © 2008 Pearson Education, Inc. (Hyperlinks are active in View Show mode) Chapter 3 – Combinational Logic Design Part 1 –
Combinational Logic Design
Overview Part 1 – Design Procedure 3-1 Design Procedure
ECE/CS 352 Digital System Fundamentals© T. Kaminski & C. Kime 1 ECE/CS 352 Digital Systems Fundamentals Spring 2001 Chapter 4 – Part 3 Tom Kaminski & Charles.
Boolean Algebra and Logic Simplification
L5 – Sequential Circuit Design
Charles Kime & Thomas Kaminski © 2004 Pearson Education, Inc. Terms of Use (Hyperlinks are active in View Show mode) Terms of Use Lecture 12 – Design Procedure.
Chap 4. Sequential Circuits
Combinational Logic Design BIL- 223 Logic Circuit Design Ege University Department of Computer Engineering.
9/15/09 - L27 CountersCopyright Joanne DeGroat, ECE, OSU1 Final Exam Review Exam Time: MONDAY o dark 30 7:30AM this room.
Optimization Algorithm
Chapter 8 -- Analysis and Synthesis of Synchronous Sequential Circuits.
Charles Kime & Thomas Kaminski © 2008 Pearson Education, Inc. (Hyperlinks are active in View Show mode) Chapter 3 – Combinational Logic Design Part 1 –
1 SOP and POS Expressions from K-maps The examples so far have all generated minimal SOP expressions. POS expressions can be formed as follows: 1.Group.
ACOE1611 Combinational Logic Circuits Reference: M. Mano, C. Kime, “Logic and Computer Design Fundamentals”, Chapter 2.
Computer Engineering (Logic Circuits) (Karnaugh Map)
Abdullah Said Alkalbani University of Buraimi
CS151 Introduction to Digital Design
SYEN 3330 Digital SystemsJung H. Kim 1 SYEN 3330 Digital Systems Chapter 9 – Part 2.
DESIGN OF SEQUENTIAL CIRCUITS by Dr. Amin Danial Asham.
1 CS 151: Digital Design Chapter 3: Combinational Logic Design 3-1Design Procedure CS 151: Digital Design.
CS151 Introduction to Digital Design Chapter 3: Combinational Logic Design 3-1 Design Procedure 1Created by: Ms.Amany AlSaleh.
CHAPTER 1 INTRODUCTION TO DIGITAL LOGIC
THE K-MAP.
SYEN 3330 Digital SystemsJung H. Kim 1 SYEN 3330 Digital Systems Chapter 6 – Part 4.
ECE 301 – Digital Electronics Logic Circuit Design (Lecture #9)
Chapter 0 – Week 2 Combinational Logic Design. What have been discussed Design hierarchy –Top – down –Bottom – up CAD HDL Logic synthesis.
SYEN 3330 Digital SystemsJung H. Kim 1 SYEN 3330 Digital Systems Chapter 7 – Part 2.
SYEN 3330 Digital SystemsJung H. Kim Chapter SYEN 3330 Digital Systems Chapter 4 -Part 1.
ECE DIGITAL LOGIC LECTURE 11: STANDARD CIRCUITS Assistant Prof. Fareena Saqib Florida Institute of Technology Fall 2015, 09/24/2015.
Contemporary Logic Design Prog. & Steering Logic © R.H. Katz Transparency No. 9-1 Chapter # 4: Programmable and Steering Logic Section 4.3, 4.4, 4.5, 4.6.
Logic Design (CE1111 ) Lecture 4 (Chapter 4) Combinational Logic Prepared by Dr. Lamiaa Elshenawy 1.
ACOE161Digital Circuit Design1 Design Of Combinational Logic Circuits.
1 Combinational Logic Design.  A process with 5 steps Specification Formulation Optimization Technology mapping Verification  1 st three steps and last.
Decoders A decoder is a logic circuit that detects the presence of a specific combination of bits at its input. Two simple decoders that detect the presence.
Combinational Logic Design. 2 Combinational Circuits A combinational logic circuit has: ♦ A set of m Boolean inputs, ♦ A set of n Boolean outputs ♦ n.
Lecture 1 Gunjeet kaur Dronacharya group of institutions.
CS151 Introduction to Digital Design Chapter 3: Combinational Logic Design 3-4 Verification 1Created by: Ms.Amany AlSaleh.
Combinational Logic Design
Overview Part 1 – Design Procedure Beginning Hierarchical Design
FIGURE 4.1 Block diagram of combinational circuit
Chapter 6 – Part 4 SYEN 3330 Digital Systems SYEN 3330 Digital Systems
SYEN 3330 Digital Systems Chapter 4 – Part 2 SYEN 3330 Digital Systems.
Homework Reading Tokheim, Section 5-10, 7-4.
SYEN 3330 Digital Systems Chapter 2 – Part 5 SYEN 3330 Digital Systems.
Chapter 5 -Part 3.
SYEN 3330 Digital Systems Chapter 2 -Part 8 SYEN 3330 Digital Systems.
SYEN 3330 Digital Systems Chapter 6 – Part 3 SYEN 3330 Digital Systems.
Circuit to Truth Table to Logic Expression
SYEN 3330 Digital Systems Chapter 2 – Part 1 SYEN 3330 Digital Systems.
Presentation transcript:

SYEN 3330 Digital SystemsJung H. Kim Chapter 3 1 SYEN 3330 Digital Systems Chapter 3

SYEN 3330 Digital Systems Chapter 3 Page 2 Design Hierarchy

SYEN 3330 Digital Systems Chapter 3 Page 3 Hierarchical Design

SYEN 3330 Digital Systems Chapter 3 Page 4 Reusable Functions and Design

SYEN 3330 Digital Systems Chapter 3 Page 5 Top-Down verses Bottom Up

SYEN 3330 Digital Systems Chapter 3 Page 6 Analysis Procedure

SYEN 3330 Digital Systems Chapter 3 Page 7 Analyze the network below F A B' C D' B E' T1T1 T2T2

SYEN 3330 Digital Systems Chapter 3 Page 8 Analysis (Continued) F A B' C D' B E' T1T1 T2T2 T3T3 F A B' C D' B E' T1T1 T2T2 T4T4 T3T3 T 3 =D’+T 2 T 4 =T1  T 3 F = A+T 4

SYEN 3330 Digital Systems Chapter 3 Page 9 Analysis (Continued) F A B' C D' B E' T1T1 T2T2 T4T4 T3T3

SYEN 3330 Digital Systems Chapter 3 Page 10 Analyze the Code Converter w x y z A B C D F1F1 F2F2 F0F0

SYEN 3330 Digital Systems Chapter 3 Page 11 Code Converter (Cont.)

SYEN 3330 Digital Systems Chapter 3 Page 12 Truth Tables from Diagrams

SYEN 3330 Digital Systems Chapter 3 Page 13 Code Converter Truth Table

SYEN 3330 Digital Systems Chapter 3 Page 14 Truth Table Fill-In

SYEN 3330 Digital Systems Chapter 3 Page 15 Finish Up Entries

SYEN 3330 Digital Systems Chapter 3 Page 16 What Does the Circuit Do?

SYEN 3330 Digital Systems Chapter 3 Page 17 Final Note (and warning)

SYEN 3330 Digital Systems Chapter 3 Page 18 Logic Design: Functional Blocks

SYEN 3330 Digital Systems Chapter 3 Page 19 Review Combinatorial Logic

SYEN 3330 Digital Systems Chapter 3 Page 20 Design Procedure

SYEN 3330 Digital Systems Chapter 3 Page 21 Code Converter Design

SYEN 3330 Digital Systems Chapter 3 Page 22 Example: BCD to Excess 3 Note: All BCD codes greater than "9" can be assigned "Don't Cares" in the K-Map. Such BCD codes are never possible.

SYEN 3330 Digital Systems Chapter 3 Page 23 Example (Cont.): BCD to Excess 3 Minimized Equations: z = D ' y=C  D + C '  D ' (exnor) x=B '  C + B '  D + B  C '  D ' w = A + B  C + B  D

SYEN 3330 Digital Systems Chapter 3 Page 24 BCD to Excess 3 Implementation

SYEN 3330 Digital Systems Chapter 3 Page 25 BCD to Excess 3