Preparations on DEPFET gate-mode Operation with Hybrid 4.1.x 17. April. 2012 Christian Koffmane 1,2 for HLL team 1 Max-Planck-Institut für Physik, München.

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Presentation transcript:

Preparations on DEPFET gate-mode Operation with Hybrid 4.1.x 17. April Christian Koffmane 1,2 for HLL team 1 Max-Planck-Institut für Physik, München 2 TU Berlin, Faculty IV of Electrical Engineering & Computer Science, Chair of Sensor and Actuator Systems

Gate-Mode Operation – (reminder)  Gated-Mode operation was proposed by Rainer Richter to encounter the Noisy Bunch Problem  in lab environment Jan Scheirich (Felix Müller) confirmed the simulation with measurements using the Mini-Matrix Setup 2 Belle II - PXD EvoMeeting C. Koffmane HLL, MPI für Physik, TU Berlin

Overview The idea is to switch the DEPFET matrix into blind mode by changing 1) the GateOn, ClearLow and ClearHigh voltages which are supplied to the Switcher 2) the changes are applied by a Trigger (TLU or Pulse Generator)# 3) different settings of the pulse generators are used to check for charge generation and charge loss during the blind periode 3 Belle II - PXD EvoMeeting C. Koffmane HLL, MPI für Physik, TU Berlin SwitcherB Readout with DCDBv2

Normal Beam-Test Setup 4 Belle II - PXD EvoMeeting C. Koffmane HLL, MPI für Physik, TU Berlin Hybrid Board FPGA Board TLU Scintillator PowerSupply PC DAQ PC LMU PowerSupply Trigger Signal DATA

Gated-Mode Operation Beam-Test Setup 5 Belle II - PXD EvoMeeting C. Koffmane HLL, MPI für Physik, TU Berlin Hybrid Board FPGA Board Agilent 81104A Agilent 81110A TLU Scintillator PowerSupply PC DAQ PC LMU PowerSupply Opto coupler HCPL 7723 Clear Hi Clear Low Gate Low Trigger Signal DATA isolated from common power network

Changing voltages 6 Belle II - PXD EvoMeeting C. Koffmane HLL, MPI für Physik, TU Berlin Voltages need ~250ns to settle  correspondents to 1 switcher 100MHz DCD-B clock

Lab measurements are ongoing  Using the described setting (pulse generators) does not change the performance of the system  Noise – is similar  Laser spot nicely visible  Measurements and analysis of first data of gate-mode sequence are ongoing (unfortunately no results yet) 7 Belle II - PXD EvoMeeting C. Koffmane HLL, MPI für Physik, TU Berlin

Summary  Gated-mode measurements in lab environment (with laser) are ongoing this week  Checking both scenarios (charge loss, charge generation)  Scanning voltages (Clear low, Gate Low, ClearGate)  Chance to measure DESY next week 8 Belle II - PXD EvoMeeting C. Koffmane HLL, MPI für Physik, TU Berlin