Advanced Implantation Detector Array (AIDA): Update & Issues Tom Davinson School of Physics The University of Edinburgh presented by Tom Davinson on behalf of the AIDA collaboration (Edinburgh – Liverpool – STFC DL & RAL)

DESPEC: Implantation DSSD Concept SuperFRS, Low Energy Branch (LEB) Exotic nuclei – energies ~ 50 – 200MeV/u Implanted into multi-plane, highly segmented DSSD array Implant – decay correlations Multi-GeV DSSD implantation events Observe subsequent p, 2p, , , ,  p,  n … decays Measure half lives, branching ratios, decay energies … Tag interesting events for gamma and neutron detector arrays

AIDA: DSSD Array Design 8cm x 8cm DSSDs common wafer design for 8cm x 24cm and 8cm x 8cm configurations 8cm x 24cm 3 adjacent wafers – horizontal strips series bonded 128 p+n junction strips, 128 n+n ohmic strips per wafer strip pitch 625  m wafer thickness 1mm  E, Veto and up to 6 intermediate planes 4096 channels (8cm x 24cm) overall package sizes (silicon, PCB, connectors, enclosure … ) ~ 10cm x 26cm x 4cm or ~ 10cm x 10cm x 4cm courtesy B.Rubio

ASIC Design Requirements Selectable gain MeV FSR Low noise keV FWHM energy measurement of implantation and decay events Selectable threshold< 0.25 – 10% FSR observe and measure low energy  detection efficiency Integral non-linearity 95% FSR spectrum analysis, calibration, threshold determination Autonomous overload detection & recovery ~  s observe and measure fast implantation – decay correlations Nominal signal processing time < 10  s observe and measure fast decay – decay correlations Receive (transmit) timestamp data correlate events with data from other detector systems Timing trigger for coincidences with other detector systems DAQ rate management, neutron ToF

AIDA: Current Status Prototype ASIC design final design review this week submission October 27 Prototype FEE design engineering concepts established (specification v.1 available) detailed engineering underway liquid cooling required (cf. AGATA digitiser module) Prototype testing fully instrumented 8cm x 8cm DSSD in-beam commissioning tests mid-2009

FEE: Block Diagram

FEE: VHDL Block Diagram

FEE: Mechanical Structure

Oustanding Issues: Time Jitter Transient signal analysis currently underway (realistic comparator design) Preamplifier risetime ( C f =0.6pF ) t r =110ns LLD threshold 0.26% 20MeV FSR 20MeV signal jitter ~0.13ns rms ( I D =1nA ), ?ns rms ( I D =100nA ) 0.2MeV signal jitter ~2.7ns rms ( I D =1nA ), ~4.0ns rms ( I D =100nA )  events will normally trigger multiple strips ‘simultaneously’ S/N improves as n 1/2 Highlights importance of minimising detector – instrumentation separation reduces noise and risetime radiation damage mitigation detector cooling Evaluate prototype & review

Oustanding Issues: Threshold Detailed simulation (with realistic component tolerances and behaviour) shows random comparator offset variations in excess of minimum threshold specification (0.25% of 20MeV FSR) - design optimisation and minimisation - design incorporates per channel offset correction via 6bit DAC - evaluate prototype & review

Outstanding Issues: AIDA Enclosure Design study by E.Reillo et al. (CIEMAT) Comparison of s/steel, Al and C fibre materials ‘Best’ option Al 0.5mm entrance window (path to ToF n-detectors) desirable Presumed satisfactory choice for Ge detectors TAS? 4  neutron detector?

AIDA Project Information Project web site Design Documents Project Technical Specification ASIC Project Specification v1.3 FEE Specification v1.0 The University of Edinburgh (lead RO) Phil Woods et al. The University of Liverpool Rob Page et al. STFC DL & RAL John Simpson et al. Project Manager: Tom Davinson

Acknowledgements This presentation includes material from other people Thanks to: Ian Lazarus & Patrick Coleman-Smith (STFC DL) Steve Thomas & Davide Braga (STFC RAL) Dave Seddon & Rob Page (University of Liverpool) Berta Rubio (IFIC, CSIC University of Valencia)