Damu, 2008EGE535 Fall 08, Lecture 21 EGE535 Low Power VLSI Design Lecture #2 MOSFET Basics

Damu, 2008EGE535 Fall 08, Lecture 22 Intrinsic and extrinsic Semiconductors Intrinsic semiconductor (no carriers at 0 0 K) Intrinsic semiconductor (n i = p i at room temp ) N type semiconductor (n i >> p i at room temp) N type semiconductor (n i >> p i at room temp) P type semiconductor (p i >> n i at room temp)

Damu, 2008EGE535 Fall 08, Lecture 23 PN Junction P- Depletion Region N type semiconductor (n i >> p i at room temp) P type semiconductor (p i >> n i at room temp) P-N Junction N+ P N

Damu, 2008EGE535 Fall 08, Lecture 24 PN Junction – Reverse Biasing Depletion width increases Reverse bias P N

Damu, 2008EGE535 Fall 08, Lecture 25 nMOSFET p- silicon L W SiO 2 Gate Source Drain Polysilicon n+ p+ silicon Bulk (substrate) t ox

Damu, 2008EGE535 Fall 08, Lecture 26 pMOSFET p-silicon L W Gate Source Drain Polysilicon n+ n well p+ Well p+silicon Bulk (substrate)

Damu, 2008EGE535 Fall 08, Lecture 27 Objective: to have current flow Objective: to have current flow L Gate Source Drain V ds I ds n P Gate Source Drain V ds I ds n P between Source and Drain between Source and Drain If this can be achieved !

Damu, 2008EGE535 Fall 08, Lecture 28 NMOS Transistor p- silicon L W SiO 2 Gate Source Drain Polysilicon n+ p+ silicon Bulk (substrate) t ox Poly SiO 2 p-type p- L SiO 2 Gate substrate t ox Capacitor Gate Substrate

Damu, 2008EGE535 Fall 08, Lecture 29 Capacitor Charging _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

Damu, 2008EGE535 Fall 08, Lecture 210 The MOS Capacitor SiO 2 Poly Holes accumulate near the top Negative Voltage to Poly + + Flat Band Accumulation + _ SiO 2 Poly

Damu, 2008EGE535 Fall 08, Lecture 211 The MOS Capacitor Very Small Positive Voltage to Poly Flat Band Depletion + _ Holes are repelled, depleting the top SiO 2 Poly

Damu, 2008EGE535 Fall 08, Lecture 212 The MOS Capacitor

Damu, 2008EGE535 Fall 08, Lecture 213 Threshold Voltage V th V gs

Damu, 2008EGE535 Fall 08, Lecture 214 Strong Inversion

Damu, 2008EGE535 Fall 08, Lecture 215 Threshold Voltage V th Much More Positive n >> Ions V >> V th Weak Inversion n<< Ions V < V th Moderate inversion n  Ions V = V th Strong inversion V th Minimum Voltage for Inversion More Positive Less Positive SiO

Damu, 2008EGE535 Fall 08, Lecture 216 Cutoff: I ds = 0 V ds V gs + + D S G I ds - - =0

Damu, 2008EGE535 Fall 08, Lecture 217 First Approximation: Threshold Voltage p- L Gate Source Drain < V th n V gs No surface electrons p- L Gate Source Drain > V th n V gs Plenty of surface electrons

Damu, 2008EGE535 Fall 08, Lecture 218 Surface Charge with V gs p- L Gate Source Drain > V th n V gs Enough electrons p- L Gate Source Drain > >V th n V gs Much More electrons

Damu, 2008EGE535 Fall 08, Lecture 219 Cutoff: I ds = 0 V ds V gs + + D S G I ds - - >V th =0 p- L Gate Source Drain > V th I ds = 0 n V gs V ds = 0

Damu, 2008EGE535 Fall 08, Lecture 220 Linear: I ds increases with V ds V gs = 0.5V V gs = 1 V V ds I ds Linear: Resistive region p- L Gate Source Drain V ds < < V gs -V th V gs > V th I ds > 0 n V ds << 2(V gs – V th ) Neglect V ds 2 I ds

Damu, 2008EGE535 Fall 08, Lecture 221Example V gs = 0.5V V gs = 1 V V ds I ds Resistive region Source Drain 1V 2V I ds > 0 n V S D 2V V V th =0.8V V gs V ds P I ds Linear : I ds

Damu, 2008EGE535 Fall 08, Lecture 222 Pinch Off: V ds = V gs -V th V gs = 0.5V V gs = 1 V V ds I ds V gs = 2 V I ds V ds = V gs -V th Nonlinear V ds = V gs – V th V gd = V gs – (V gs –V th ) = V th

Damu, 2008EGE535 Fall 08, Lecture 223 Saturation: I ds independent of V ds For V ds >V gs -V th Vds = Vgs-V th Velocity saturation: I ds constant V ds > V gs -V th V gs > V th I ds sat Source Drain n+ p-silicon Pinch Off extends No channel !! V ds I ds I ds Saturation

Damu, 2008EGE535 Fall 08, Lecture 224 Regions of Transistor Operation 1. Linear region : V GS > V th V DS < V GS – V th V th - threshold voltage 2. Saturation region: V GS > V th V DS  V GS - V th Deep Triode V ds I ds I ds Saturation resistor I-V curve Triode region Saturation region V gs =0.5V V gs =1V V gs =2V X X X a b c

Damu, 2008EGE535 Fall 08, Lecture 225 Current Equation

Damu, 2008EGE535 Fall 08, Lecture 226 Channel Length Modulation > V gs -V th > V th I ds Source Drain n+ p-silicon Pinch Off extends channel length reduces V ds I ds I ds Saturation -V A   0.02V -1

Damu, 2008EGE535 Fall 08, Lecture 227PMOSFET

Damu, 2008EGE535 Fall 08, Lecture 228 PMOSFET: No current L Gate Source Drain _ I ds = 0 N P |V gs | > |V th | V ds = 0 V th Negative voltage V ds Negative voltage

Damu, 2008EGE535 Fall 08, Lecture 229 PMOSFET: Current flow L Gate Source Drain _ I ds > 0 N P |V gs | > |V th | | V ds | > 0 V gs & V ds Negative voltages

Damu, 2008EGE535 Fall 08, Lecture 230 PMOS Transistor 1. Linear region : |V GS | > |V th | V th - threshold voltage (Min for inversion layer) |V DS | << |V GS – V th | |V DS | < |V GS – V th | 2. Saturation region: |V GS | > |V th | |V DS |  |V GS - V th | Deep Triode Triode

Damu, 2008EGE535 Fall 08, Lecture 231 MOSFET Symbols