Lab 3 MOSFET Capacitance EC538 Selected Topics in Electronics Lab 3 MOSFET Capacitance Eng. Nihal Tawfik

Outline MOSFET Models BSIM Family MOSFET Capacitance Gate Capacitance Diffusion Parasitic Capacitance

MOSFET Models Level 1 Known as Shichman-Hodges Model (1968). Accurate only for long channel devices Level 2 MOS2 It incorporates second order effects, computationally complex. Level3 MOS3 A semi-empirical model includes second order effects due to narrow width and short channel lengths Computationally efficient compared to Level2 BSIM Models BSIM stands for Berkeley Short-channel IGFET Model. The BSIM1 model was developed by Sheu, Scharfetter, Poon and Hu at Berkeley in 1984, for higher accuracy modeling of short-channel devices.  Other popular MOSFET Models: Philips MOS9, Philips MOS 11, EKV, HiSIM, SP2000… Long channel (L>1u)

BSIM Family

MOSFET Capacitances MOS capacitance are broadly classified into: Gate Capacitance Due to oxide thickness Essential in forming the channel. Diffusion Capacitance Due to pn junction depletion layer between the source and body and also between drain and body called: Csb, Cdb. Unwanted, parasitic Capacitance.

Intrinsic Capacitance Gate Capacitance Gate Capacitance Intrinsic Capacitance Overlap Capacitance Cgol Cgsol Cgdol Depends on the mode of operation:

P7: Gate Oxide Intrinsic Capacitance A 90 nm long transistor has a gate oxide thickness of 16 Å. What is its gate capacitance per micron of width?

P9: Overlap Capacitance In the three dimensional view of a silicon n- channel MOS transistor shown below, δ= 20 nm. The transistor is of width 1 µm. The depletion width formed at every p-n junction is 10 nm. The relative permittivity of Si and SiO2 respectively, are 11.7 and 3.9, and Ɛ0 = 8.9 X 10-12F/m. Find the gate source overlap capacitance.

Diffusion Parasitic Capacitance The grading coefficient m is a unit-less number and typically about 0.5. Its value depends on the nature of the P-N junction. If the P region changes abruptly (a step change) to the N region at the junction, m = 0.5 (square root) and the junction is called an abrupt P-N junction. If the P region changes linearly into the N region (graded junction) at the junction, m = 0.333 (cubed root). High voltage power diodes often go from P to intrinsic semiconductor to N semiconductor (PIN diode) in which case m is close to 0, a constant capacitance.  NOTE: Cjbs has units of Capacitance/area while Cjbssw has units of capacitance/length.

Level3 MOS Diffusion Capacitance Parameters * Long channel models from CMOS Circuit Design, Layout, and Simulation, * Level=3 models VDD=5V, see CMOSedu.com * .MODEL N_1u NMOS LEVEL = 3 + TOX = 200E-10 NSUB = 1E17 GAMMA = 0.5 + PHI = 0.7 VTO = 0.8 DELTA = 3.0 + UO = 650 ETA = 3.0E-6 THETA = 0.1 + KP = 120E-6 VMAX = 1E5 KAPPA = 0.3 + RSH = 0 NFS = 1E12 TPG = 1 + XJ = 500E-9 LD = 100E-9 + CGDO = 200E-12 CGSO = 200E-12 CGBO = 1E-10 + CJ = 400E-6 PB = 1 MJ = 0.5 + CJSW = 300E-12 MJSW = 0.5 The default value for Area and perimeter are zeros. Hence, underestimating the parasitic delay in the mosfet.

BSIM4 MOS Diffusion Capacitance Parameters * Short channel models from CMOS Circuit Design, Layout, and Simulation, * 50nm BSIM4 models VDD=1V, see CMOSedu.com * .model N_50n nmos level = 54 +pbs = 1 cjs = 0.0005 mjs = 0.5 pbsws = 1 +cjsws = 5e-010 mjsws = 0.33 pbswgs = 1 cjswgs = 5e-010 +mjswgs = 0.33 +pbd = 1 cjd = 0.0005 mjd = 0.5 +pbswd = 1 cjswd = 5e-010 mjswd = 0.33 pbswgd = 1 +cjswgd = 5e-010

P8: Diffusion Parasitic Capacitance Calculate the diffusion parasitic Cdb of the drain of a unit- sized contacted nMOS transistor in a 0.6 m process if the size of the diffusion contact is 4x5 when the drain is at 0V and at VDD = 5 V. Assume the substrate is grounded. The transistor characteristics are CJ = 0.42 fF/m2, MJ =0.44, CJSW = 0.33 fF/m, MJSW = 0.12, and 0 = 0.98 V at room temperature. Designer often express a process by its feature size. Lambda is half of the minimum drawn channel length transistor. Process size:90nm 65nm