Feature-level Compensation & Control F LCC Lithography April 5, 2006 A UC Discovery Project

FLCC 04/05/2006 FLCC - Lithography 2 Current Milestones Establish industry acceptable Process-EDA test structures (LITH Y3.1) Refine test-patterns designs to measure key model parameters while mitigating chip test area, minimize mask-writing time, and maximize simplicity in quantitative interpretation. Create design-rule qualifiable test structures for PPC calibration (LITH Y3.2) Create 2-D test patterns that are compatible with design rules and superior to device features in identifying and quantifying process parameters for pre-compensation treatments. Test electrical PSM-PI and explore zero-foot-print electronic versions (LITH Y3.3) Evaluate wafer performance of electrical probe PSM-PI for focus mapping. Combine parameter specific interferometric-probe targets with electronic detection and RF communication for in situ stepper measurements. Evaluate Pattern-Matching for predicting device variation hot-spots (LITH Y3.4) Develop maximum lateral impact functions for locating gates with high levels of device variation and correlate results with wafer experiments and the Quantitative Yield Simulator being developed on SRC/DARPA support. Prototype Pattern-Matching for predicting interconnect delay variation (LITH Y3.5) Develop maximum lateral impact functions and net-list tracking software for locating, quantifying and summing variations in interconnect delay due to residual process non- idealities.

FLCC 04/05/2006 FLCC - Lithography 3 Multi-phase mask patterns derived from high numerical aperture theory to sample illumination polarization states. Used to assess layout sensitivity. Multiple patterns work together to characterize polarization Backside pinhole enables frequency selection and full pupil-fill measurement Greg McIntyre PhD May 06 PSM Polarimetry: Monitoring polarization at 193nm high-NA with phase shift masks

FLCC 04/05/2006 FLCC - Lithography 4 The Problem Leverage high-NA vector effects to create a polarization dependent signal in photoresist

FLCC 04/05/2006 FLCC - Lithography 5 Mask 1: Experimental results – On axis

FLCC 04/05/2006 FLCC - Lithography 6 Mask 2: Full pupil-fill characterization Frequency selection with pinhole array on backside of reticle 513 pinhole / cluster combinations 3 types of ‘OPC’ 2 pinhole sizes 9 programmed pinhole misalignment 9 programmed process misalignment 5 calibration & 4 test exposed polarization states Calibration Test

FLCC 04/05/2006 FLCC - Lithography 7 Electrical Test Monitors Y polarization analyzer H polarization V polarization Aerial image Contour at resist threshold Metal (or poly) Oxide (or Si) Final pattern in metal or poly Closed Circuit Open Circuit Contour at resist threshold Double exposure enables electrical signal and simplifies data collection

FLCC 04/05/2006 FLCC - Lithography 8 Fast-CAD and Novel Targets Pattern Matching Extensions High-NA Polarization Attenuated-PSM Strong Off-Axis Double Dipole Exposure Novel Targets Electrical Probing Electronic detection Student-Test Mask Coordinator Juliet Holwill CAD Student

FLCC 04/05/2006 FLCC - Lithography 9 Two Problems Under Study The pattern matcher is a fast tool which must be extended to advancing optical technologies such as off-axis illumination, OPC treated layouts and attenuated phase masks in order to remain competitive. =+ Pattern and probe aberration monitors are modified for use as double exposure and single exposure electrical test structures.

FLCC 04/05/2006 FLCC - Lithography 10 Simulation Results for Off-Axis High-NA and Off-Axis Polarization Pattern Matching The layouts used for these experiments

FLCC 04/05/2006 FLCC - Lithography 11 Pattern Matching for Attenuated Phase Shift Masks Original Layer Matching Attenuated Layer Matching 0  layer: match with weight  layer: Match with weight Add a 180  Layer

FLCC 04/05/2006 FLCC - Lithography 12 Pattern Matching for OPC Treated Layouts The second algorithm uses: More fragmentation More ripples Smaller edges 150 iterations, compared to 11 for the first Only a small change in coma match factors

FLCC 04/05/2006 FLCC - Lithography 13 Double Exposure Treatments for Complementary Dipole Exposure Two different splits for complementary dipole layouts from Eric Hendrickx, IMEC

FLCC 04/05/2006 FLCC - Lithography 14 Single Exposure Electrical Test Structures 0˚ 90˚ 180˚ 0.03 Defocus 0.00 Defocus

FLCC 04/05/2006 FLCC - Lithography 15 Extension of Fast-CAD Pattern Matching for Assessing Across Chip Interconnect Variation Capacitance Variation Function Multiple Mask Level Operator More Wiring to Follow? Follow Wiring and Location yes Done no Quantify and Paraeto Physical Causes –Alignment, Plasma Etch, slit position, CMP dishing variation Assess feasibility of software functions –Net List, Chip Location Define Architecture Eric Chin New Chip Level Tools to Find and Quantify Location Dependent Variations of R and C

FLCC 04/05/2006 FLCC - Lithography 16 Identifying Pattern Match Results in Design Pattern Match Location

FLCC 04/05/2006 FLCC - Lithography 17 Proposed Design Flow with Pattern Matcher Parasitic Extraction FAIL, Respin Design PASS, Proceed to Next Step Timing Analysis Pattern Matcher Modify Rs, Cs

FLCC 04/05/2006 FLCC - Lithography 18 Modification of Extracted Parasitics Original New Pattern Match Calculate Edge Movements Determine Δ R, Δ C Modify Extracted Values

FLCC 04/05/2006 FLCC - Lithography 19 Experiments on Sources of Variation Vary: Focus; Dose; Illumination; OPC Wojtek Poppe SRC/DARPA PhD Project: Quantitative Yield Simulator Collaborating on Verification on FLCC with Cypress 2005 Test Mask Design 4 Mask NMOS at Cypress Measure Vt and Leakage at UCB

FLCC 04/05/2006 FLCC - Lithography Mask NMOS Chip Layout

FLCC 04/05/2006 FLCC - Lithography Vanilla CMOS Wafer Fabrication at Cypress

FLCC 04/05/2006 FLCC - Lithography 22 Design-Rule Qualifiable Test-Structures for Nominal Process Parameters Challenge: –OPC/PPC parameters must be tuned to the Fab. often even without knowledge of the NA, illumination, etc. (Just Design Rules) Hypothesis: –Versions of 2D Test Patterns could be implemented that pass DRC and are significantly (3X) superior to device features in isolating and quantifying OPC/PPC parameters. Research Strategy: –Implement Patterns similar to FLCC Test Patterns with feature sizes ~ 0.5 /NA. –Use simulation to optimize promising layouts –Validate in collaboration with industry

FLCC 04/05/2006 FLCC - Lithography 23 Current Milestones Establish industry acceptable Process-EDA test structures (LITH Y3.1) Produce a multi-student test reticle with next-generation refined test-patterns designs for CMP, lithography, and etching. Create design-rule qualifiable test structures for PPC calibration (LITH Y3.2) Map existing test structure examples into design rules and assess sensitivity/orthogonality. Test electrical PSM-PI and explore zero-foot-print electronic versions (LITH Y3.3) Develop layout strategy for locating 2D test patterns and optimize the optical interferometric 2D aberration patterns for achievable detector characteristics. Evaluate Pattern-Matching for predicting device variation hot-spots (LITH Y3.4) Correlate match factors with feature edge movement in SPLAT and circuit performance change in the Quantitative Yield Simulator being developed on SRC/DARPA support. Prototype Pattern-Matching for predicting interconnect delay variation (LITH Y3.5) Build the code for tracking geometry along the net-list, develop geometry impact functions for pattern dependent CMP and evaluate with a test scenario.

FLCC 04/05/2006 FLCC - Lithography 24 Future Milestones Develop and test 2D test structures for linking process with EDA. (LITH 4.1) Create, design, layout, fabricate, and experimentally characterize physics-based 2D patterns that reveal and quantify presence of specific phenomena ranging from optical to laser thermal annealing in embodiments that may include SEM, electrical or electronic based measurements and that may be design-rule qualifiable. Establish industry acceptable Pattern-Matching for predicting device variation hot-spots (LITH Y4.2) Extend to advanced forms of high-NA, high off-axis, polarization and immersion lithography the effectiveness of maximum lateral impact functions for locating gates with high levels of device variation and correlate results with wafer experiments and the Quantitative Yield Simulator being developed on SRC/DARPA support. Evaluate Pattern-Matching for predicting interconnect delay variation (LITH Y4.3) Assess effectiveness of prototype software based on maximum lateral impact functions and net-list tracking software for locating, quantifying and summing variations in interconnect delay due to residual process non-idealities.