FE-I4 chip development status ATLAS Upgrade, R.Kluit

MOU Agreement for sharing FE-I4 IP in the collaboration. All Data stored in central repository What will be stored central. Use of IBM kits and libraries. Share parts to others : NO, unless granted and added in MOU What can be used by Nikhef: -current reference -for gas det. :all other blocks can be used. When referring to FE-I4 USA: Lawrence Berkeley National Laboratory Germany: Bonn University Physikalisches Institut Italy: Instituto de Fisica Nucleare (INFN) Genova France: Center for particle physics of Marseilles (CPPM) The Netherlands: National Institute for Subatomic Physics (NIKHEF) France: Laboratory of the Linear Accelerator (LAL), Orsay.

FE-I4 work Prototype submitted March Parts : – LVDS & LDO (Bonn) – SEU circuits (Saclay) – Pixel FE array 14x61 with control(LBNL) – Command dec. (Gevova) – current ref. (Nikhef) Matching Si-sensor in development Test boards developed by Bonn Physics simulation, readout => Bonn Now: try out of multi-site design- data-management software. (needs license = €’s) Active participants: LBNL : M-G. Sciverez: +2 Bonn: M. Barbero + ph: Genova: Darbo + Beccerle: 1 Marseille: Rozanov :+1 Nikhef: ph. …. :+1.2 R. Kluit + J-D. Schipper

Nikhef contr. Current reference (completed) Behavioral (high level) design of chip blocks (goal) Pixel logic; evaluate options: – memory/pixel: group 2, 4, 8 => evaluate 8p 8m – BID distribution or counter/pixel – J-D Schipper: Verilog design of 8 pixel logic region Pixel FE in I4 dual threshold: analog threshold + TOT: only large pulses are stored. “Large” pulse readout with Neighbor hits. “Small” pulse only is not read out

11-Feb-08M. Garcia-Sciveres -- pixel architecture5 Region architecture overview 4-bit TOT Share timing bits – but keep charge info /pixel Reduce data transfer – Destroy unwanted hits locally “Hide” global memory in pixel array 8-bit TOT All pixels treated as independent 1 Timestamp, 2 charges, 2 neighbors Region local memory 1 Timestamp, 2 charges, 2 neighbors Global memory (distributed) Pixel group Global memory at bottom of chip Read out triggered pixels only triggered hits only Read out All hits All hits All hits Each pixel OLD (FE-I3)NEW (Region) 1 charge 1 timestamp Real time data transfer () This transfer places a hard limit on rate capability