1 Interstrip resistance in silicon position-sensitive detectors E. Verbitskaya, V. Eremin, N. Safonova* Ioffe Physical-Technical Institute of Russian Academy of Sciences St. Petersburg, Russia *also Saint-Petersburg Electrotechnical University “LETI”, Russia N. Egorov, S. Golubkov Research Institute of Material Science and Technology (RIMST) Zelenograd, Russia 15 RD50 Workshop CERN, Geneva, November 16-18, 2009

2 Outline Motivation Physical model of interstrip resistance Experimental results on interstrip resistance in as- processed Si detectors Influence of nonequilibrium carrier generation R IS in n-type FZ and CZ Si samples Conclusions E. Verbitskaya et al., 15 RD50 Workshop, CERN, Geneva, Nov 16-18, 2009

3 Motivation Current subjects:  Development of operational model for voltage terminating structure (VTS) and current terminating structure (CTS, edgeless detectors)  Strip detector performance at SLHC: very high fluences and enhanced bulk generated current  Noise performance of spectroscopic strip detectors (GSI, Darmstadt) E. Verbitskaya et al., 15 RD50 Workshop, CERN, Geneva, Nov 16-18, 2009

4 Special design of test structures FZ n-Si,  >5 k  d = 300  m V fd  20 V E. Verbitskaya et al., 15 RD50 Workshop, CERN, Geneva, Nov 16-18, 2009 p + -n-n + structure - area 1x1 mm 2 Strips: two interpenetrating “combs”: - pitch 25  m  increased length of interstrip gap  equivalent to 4 cm strips 1 2

5 Physical model  1 =  2 - potentials at the strips E. Verbitskaya et al., 15 RD50 Workshop, CERN, Geneva, Nov 16-18, 2009 Distortion of symmetric distributions of potential and electric field may stimulate excess current flow between strips Components that control interstrip resistance R IS : - surface leakage - interface current

6 Measurements of interstrip gap characteristics E. Verbitskaya et al., 15 RD50 Workshop, CERN, Geneva, Nov 16-18, 2009 U 1 – bias voltage applied to p-n junction U 2 – bias voltage between the strips

7 I-V characteristics of interstrip gap I = I d + I inst E. Verbitskaya et al., 15 RD50 Workshop, CERN, Geneva, Nov 16-18, 2009 I d – strip dark current I inst – interstrip current FZ n-Si, # WP 3-6-2

8 E. Verbitskaya et al., 15 RD50 Workshop, CERN, Geneva, Nov 16-18, 2009 Current flow in interstrip gap   U 2cr  with U 1   U 2cr - range of bias voltage in which I inst is small hole drift  U 2cr

9 Interstrip current I inst I inst (U 2 ): dark current is subtracted  Regions with different slopes:  A and A*: R  = (dI inst /dU 2 ) -1 - ohmic isolation resistance, independent on U 1, related mainly with surface leakage  B: current step  I inst   I inst and dI inst /dU 2  as U 1  E. Verbitskaya et al., 15 RD50 Workshop, CERN, Geneva, Nov 16-18, 2009 Interstrip resistance: R IS = dU 2 /dI inst

10 Origin of interstrip current step  I inst  ≠  2 Current switching – redistribution of strip hole currents In detector: Switching acts as negative feedback  recovery of potential balance E. Verbitskaya et al., 15 RD50 Workshop, CERN, Geneva, Nov 16-18, 2009 R sw = (dI inst /dU 2 ) -1 in  I inst region

11 Interstrip resistance vs bias voltage E. Verbitskaya et al., 15 RD50 Workshop, CERN, Geneva, Nov 16-18, 2009 R sw = dU 2 /dI is at U 2  0 R sw  with U 1  R   200 G  irrespective to U 1 and at ±U 2 R   R sw

12 Influence of nonequilibrium carrier generation Carrier generation: - by LED illuminating p + side - white light on n + side E. Verbitskaya et al., 15 RD50 Workshop, CERN, Geneva, Nov 16-18, 2009 I = I ph + I inst

13 Influence of nonequilibrium carrier generation on R IS  R  and R sw  with carrier generation  R    p + illumination – high n and p under SiO 2  R sw at carrier generation: no dependence on U 1 – switching is controlled by photocurrent rather than dark current E. Verbitskaya et al., 15 RD50 Workshop, CERN, Geneva, Nov 16-18, 2009  Ratio of R sw is about one half of current ratio since ½ of a total structure current is switched

14 Influence of Si type E. Verbitskaya et al., 15 RD50 Workshop, CERN, Geneva, Nov 16-18, 2009 Similar behavior of I inst vs. U 1 and U 2 FZ n-Si CZ n-Si

15 Comparison of I inst for different Si types   U 2cr is smaller in CZ Si   U 2 corresponding to  I inst is smaller in CZ Si  R  is similar E. Verbitskaya et al., 15 RD50 Workshop, CERN, Geneva, Nov 16-18, 2009

16 Comparison of R sw for different Si types Parameterization: R sw = A - B(U 1 ) 0.5 R sw is smaller in CZ Si FZ: R sw = 7.2  – 5.9  10 9 (U 1 ) 0.5 CZ: R sw = 2.5  – 2.2  10 9 (U 1 ) 0.5 E. Verbitskaya et al., 15 RD50 Workshop, CERN, Geneva, Nov 16-18, 2009  R sw depends on bulk generation current

17  Different wafer orientation  Detectors with different configuration  Study of irradiated Si detectors Future studies E. Verbitskaya et al., 15 RD50 Workshop, CERN, Geneva, Nov 16-18, 2009

18 Conclusions  The factors that define interstrip isolation resistance are: - surface leakage, - interface current, - new mechanism - distortion of symmetric potential distribution at the strips and switching of strip currents.  Switching of strip currents is a negative effect since it decreases interstrip isolation. This effect may control interstrip resistance rather than ohmic conductance between the strips.  R  is about 200 G  irrespective to the bias voltage while R sw is bias dependent and decreases with bias voltage rise down to few G  E. Verbitskaya et al., 15 RD50 Workshop, CERN, Geneva, Nov 16-18, 2009 Results are partially published in: V. Eremin et al., Semiconductors 43 (2009) 796.

19 This work was made in the framework of RD50 collaboration and supported in part by: RF President Grant # Fundamental Program of Russian Academy of Sciences on collaboration with CERN Acknowledgments Thank you for attention! E. Verbitskaya et al., 15 RD50 Workshop, CERN, Geneva, Nov 16-18, 2009