PXD DAQ News S. Lange (Univ. Gießen) Belle II Trigger/DAQ Meeting (Jan 16-18, 2012, Hawaii, USA) Today: only topics important for CDAQ - GbE Connection to CDAQ - DATCON All other new discussions and results  Vienna PXD+SVD Workshop

2 Connection of PXD DAQ (ATCA) to CDAQ (EVB #2)

3 Send PXD data by GbE to CDAQ  Plan A: GbE by PowerPC (Linux) UDP or TCP/IP software  Plan B (only if plan A does not work)  GbE by optical link UDP hardware  GbE by siTCP TCP/IP hardware  Related questions:  do we need a GbE switch ARISTA 7500 ? (150kEuro) (see Yamagata-san‘s talk at Yugawara)  should ATCA do PXD subevent building, or not?  requires ATCA backplane discouraged by PAC report  needs 3rd Ph.D. student (decision about BMBF application expected 06/2012)  [SVD+PXD] subevents required by GPU farm

4 1. Send GbE by PowerPC  Embedded PPC on Virtex-4 or -5  3% PXD occupancy = 540 MB/s factor 3 reduction by HLT factor 10 reduction by ATCA (design goal of algorithm) = 18 MB/s required  TCP/IP tested o.k. ~26 MB/s achieved at IHEP on PPC405 on Virtex-4 (CN Vers. 1) (~22.5 MB/s in Giessen by Björn Spruck, CN Vers. 2) Compute Node Version #2 Virtex-4 FX60 Compute Node Version #3 Virtex-5 FX70T

5 2. Send GbE by optical link  Only necessary, if design reduction factor not achievable  Guest project at Giessen Greg Korcyl (Panda) 2-3 weeks in August weeks in November 2010 work continues in Krakow with a CN Vers. 2  UDP  So far optical links, but copper GbE should be possible work in progress  in any case, can be used as Bonn  Giessen interface (DATCON sending SVD ROI to ATCA)  See next 2 slides: - test system - test results

6 Test System optical RJ45

7 Test Results (report by G. Korcyl, )  Sucessfully implemented and tested  DHCP address acquisition  Address based filtering  ARP discovery  Ping (just to check the status)  Stat: a module that sends a frame each few seconds with current statistics, (rx, tx, frames counters etc.)  DataRX: a module to receive detector data receives all the frames sent to a given UDP port and stores the data to the CN memory  Loopback test (G. Korcyl and B. Spruck)  Packet sent from PC received by fpga logic  Data transferred to the CN memory  Application running on PPC gets notified that new has been stored in the memory  Application initiates the transmission of the data back to fpga logic  TX module of fpga constructs a packet and sends it back to the PC  Conclusions:  solution is working but for the moment is not stable (bytes get lost, garbage bytes appear etc.)  achieved rate at <60 MB/s

8 2. Send GbE by siTCP  Only necessary, if design reduction factor not achievable  FPGA TCP/IP firmware - supported by KEK (Tomohisa Uchida-san, Manobu Tanaka-san) many thanks for their help - licenses are commercial, 8000,- Yen per 1 MAC addr  Test by Thomas Geßler at KEK, 2 weeks in Dec 2011  tested sucessfully on ML403 (Virtex-4 FX20) and CN Vers. 3 (Virtex-5 FX70T)  resources usage very small 9% Slice Registers, 7% Slice LUTs, 9% BRAM  >100 MB/s achieved from CN3 to PC  disadvantage: only 1 connection open at a time  generates overhead, if packets are send to different EVB receivers (open, send, acknowledge, close = 4 packets for 1 packet payload) -> principally only 1 EVB (fixed MAC addr) -> there is no advantage compared to UDP most probably ruled out

9 Proposal for Discussion: 1:1 MAC addr assignment RJ45 UDP On PC: - UDP checking algorithm (package dropped?) - conversion from UDP to TCP/IP - PXD subevent builder No fixed MAC addr assignment RJ45 TCP/IP ATCAEVB #2 /40/~10

DATCON Bonn System for SVD ROI J. Dingfelder, C. Marinas, M. Schnell

11 Data Concentrator (DatCon) for data reduction with an FPGA-based track finding algorithm Input: 42 optical links with 1.5 Gbps line rate Output: One Ethernet and two 6.25 Gbps high speed links Hardware : 12 AMC cards in an ATCA shelf with 3 carrier boards Data Concentrator: Concept and implementation

12 Custom protocol "BELLE II Link" for data transmission Aurora protocol for internal high speed data routing Multiplexer and Memory Management Unit for data collection and storage "Fast Hough Transformation" or "cellular automaton" implemented in FPGA for track finding Hardware solution and future plans

Mahalo.