Insert project logo Gossipo3 & 4 3 rd Prototype of a front-end chip for 3D MPGD Project outline. 7/2/20161GOSSIPO3 prototype.

Slides:



Advertisements
Similar presentations
Line Efficiency     Percentage Month Today’s Date
Advertisements

Unit Number Oct 2011 Nov 2011 Dec 2011 Jan 2012 Feb 2012 Mar 2012 Apr 2012 May 2012 Jun 2012 Jul 2012 Aug 2012 Sep (3/4 Unit) 7 8 Units.
GOSSIPO-2 chip: a prototype of read-out pixel array featuring high resolution TDC-per-pixel architecture. Vladimir Gromov, Ruud Kluit, Harry van der Graaf.
Gossipo-3: a prototype of a Front-end Pixel Chip for Read-out of Micro-Pattern Gas Detectors. TWEPP-09, Paris, France. September 22, Christoph Brezina.
1 TimePix-2 a new and fast general-purpose MPGD readout pixel chip Jan Timmermans, Nikhef MPGD/RD-51 Workshop Nikhef, Amsterdam The Netherlands April 16,
R. Kluit Nikhef Amsterdam R. Kluit Nikhef Amsterdam Gossopo3 3 rd Prototype of a front-end chip for 3D MPGD 1/27/20091GOSSIPPO3 prototype.
Technical status of the Gossipo-3 : starting point for the design of the Timepix-2 March 10, Vladimir Gromov NIKHEF, Amsterdam, the Netherlands.
P. Name Nikhef Amsterdam Electronics- Technology Vladimir Gromov, NIKHEF, Amsterdam. GOSSIPO-3 Meeting May 25, Layout of the Front-end.
GOSSIPO-3: Measurements on the Prototype of a Read- Out Pixel Chip for Micro- Pattern Gas Detectors André Kruth 1, Christoph Brezina 1, Sinan Celik 2,
R. Kluit Nikhef Amsterdam R. Kluit Nikhef Amsterdam Gossipo3 3 rd Prototype of a front-end chip for 3D MPGD 1/27/20091GOSSIPO3 prototype.
Jan 2016 Solar Lunar Data.
Scholarship Submission Calendar

Q1 Jan Feb Mar ENTER TEXT HERE Notes


Project timeline # 3 Step # 3 is about x, y and z # 2
Average Monthly Temperature and Rainfall





Mammoth Caves National Park, Kentucky
2017 Jan Sun Mon Tue Wed Thu Fri Sat
Timeline PowerPoint Template



Gantt Chart Enter Year Here Activities Jan Feb Mar Apr May Jun Jul Aug
Q1 Q2 Q3 Q4 PRODUCT ROADMAP TITLE Roadmap Tagline MILESTONE MILESTONE
Free PPT Diagrams : ALLPPT.com

Proposed Strategic Planning Process for FY 2013/14 thru FY 2015/16

Step 3 Step 2 Step 1 Put your text here Put your text here
Calendar Year 2009 Insure Oklahoma Total & Projected Enrollment
MONTH CYCLE BEGINS CYCLE ENDS DUE TO FINANCE JUL /2/2015
Jan Sun Mon Tue Wed Thu Fri Sat
2009 TIMELINE PROJECT PLANNING 12 Months Example text Jan Feb March



©G Dear 2008 – Not to be sold/Free to use

Electricity Cost and Use – FY 2016 and FY 2017


©G Dear 2010 – Not to be sold/Free to use
Text for section 1 1 Text for section 2 2 Text for section 3 3
Text for section 1 1 Text for section 2 2 Text for section 3 3
Text for section 1 1 Text for section 2 2 Text for section 3 3
Text for section 1 1 Text for section 2 2 Text for section 3 3
Q1 Q2 Q3 Q4 PRODUCT ROADMAP TITLE Roadmap Tagline MILESTONE MILESTONE
Free PPT Diagrams : ALLPPT.com


Text for section 1 1 Text for section 2 2 Text for section 3 3
Text for section 1 1 Text for section 2 2 Text for section 3 3
Text for section 1 1 Text for section 2 2 Text for section 3 3
Text for section 1 1 Text for section 2 2 Text for section 3 3
Text for section 1 1 Text for section 2 2 Text for section 3 3
Text for section 1 1 Text for section 2 2 Text for section 3 3
Project timeline # 3 Step # 3 is about x, y and z # 2
TIMELINE NAME OF PROJECT Today 2016 Jan Feb Mar Apr May Jun

2009 TIMELINE PROJECT PLANNING 12 Months Example text Jan Feb March
Skull & Spirit Creature
Globus-M2 will be constructed by the end of 2015
Q1 Q2 Q3 Q4 PRODUCT ROADMAP TITLE Roadmap Tagline MILESTONE MILESTONE
Presentation transcript:

insert project logo Gossipo3 & 4 3 rd Prototype of a front-end chip for 3D MPGD Project outline. 7/2/20161GOSSIPO3 prototype

insert project logo 1 st prototype Before Gossipo4 submission (~14mm 2 ), test basic circuits in intermediate prototype: Gossipo3 (~1mm 2 ): Preamp (with bias) Discriminator (with bias) Logic + TDC/oscillator VDD regulator. Other features ? MOSIS MPW, July 20 th 7/2/2016GOSSIPO3 prototype2

insert project logo Time Scale (2) GOSSIPO3 prototype37/2/2016 ExtraApr 2009 May 2009Jun 2009Jul 2009Aug 2009 Sep 2009Oct 2009 Nov 2009 Dec 2009Jan 2010 Gossipo3 tape-out =============== 20th Gossipo4 tape-out =========== 9th preamp design ======== preamp layout & verification +bias ======== Discriminator Design +bias ======== Discriminator Layout & verification +bias ======== Threshold DAC Design +bias ======== Threshold DAC Layout & verification +bias Pixel Logic (& TDC) design ======== Pixel Logic (& TDC) layout & verification ============= Oscillator LDO design ============= Oscillator LDO layout & verification =========== pad ring and I/O cells =========== Internal buffers === Ingrid preamp design ======== Ingrid preamp layout & verification ===== Chip Intrgration, layout & verification ===========

insert project logo Part+StatusWorkdesignlayoutDesigners PreampConcept designDesign, simulation, implementationAndre(+Vlad) DiscriminatorConcept designVladimir Threshold DAC/opampproposalVlad. TDC oscillatorPresent designStability- and uniformity optimizationChris. B Power distribution + regulator design specifySee TDC oscillatorChris. B TDC & countersConcept designSinan + Vlad Fast-ORplanNikhef ReadoutPlan, like gossipo2New designNikhef Bias blocks--New designNikhef&Bonn I/O pads & buffersSome of gossipo2Copy ?share Signal distribution/buffers --Nikhef(?) INGRID preamp ?RequestedNew item: specify & designBonn (?) Chip integration--Full chip assembly & verificationNikhef Work partitioning (preliminary) 7/2/2016GOSSIPO3 prototype4