1 Instructions are stored in a memory called instruction memory To execute each instruction, we get the instruction out of memory, store in a register.

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Presentation transcript:

1 Instructions are stored in a memory called instruction memory To execute each instruction, we get the instruction out of memory, store in a register called instruction register (may be more than one single register of n-bits depending on the number of words in an instruction), and carry out operations on data path to achieve the desired result It may take more than one cycle to execute an instruction Each cycle is called phase (or state) in instruction execution Actions in one cycle is stored in one nano-instruction For each instruction (micro-instruction per book), multiple nano instructions, one for each phase, are stored in nano_inst_mem Instructions are fetched one at a time pointed by a counter, called program counter For each instruction, nano instructions are fetched from nano memory, using a counter called nano-program counter Instruction Storage and Usage

2 Program memory has –A PC –Memory –Mechanism to change PC Adding Program Memory Nano Inst Mem NPC WNAD INAD NAddr Control Inst Mem PC WIAD IIAD IAddr INST Mem Unit WM EM Data Addr RM WDAD ALUALU OpCode Reg File WA WR RA2RA1 Input EI Output WOUT EALU M- Reg EMR SHIFTSHIFT SC Cond Code

3 ALU generate status bits like –carry, overflow, sign, and zero –zero=1 means result from ALU is zero These bits can be used to change flow of program –A new address is generated using CCs Adding Conditional Branches Nano Inst Mem NPC WNAD INAD NAddr Control Inst Mem PC WIAD IIAD IAddr INST Mem Unit WM EM Data Addr RM WDAD ALUALU OpCode Reg File WA WR RA2RA1 Input EI Output WOUT EALU M- Reg EMR SHIFTSHIFT SC Cond Code

4 Program change flow For example –If.. Then… Else Condition codes determine flow PC is changed Conditional Branch Instruction Nano Inst Mem NPC WNAD INAD NAddr Control Inst Mem PC WIAD IIAD IAddr INST Mem Unit WM EM Data Addr RM WDAD ALUALU OpCode Reg File WA WR RA2RA1 Input EI Output WOUT EALU M- Reg EMR SHIFTSHIFT SC Cond Code