C. Murad Özsert Intel's Tera Scale Processor Architecture

Agenda  Introduction  Intel Tera-scale Computing Research Program  Architecture of Intel’s Teraflops Research Processor –Power Management –Performance  Conclusion

Why Multi-core?

Intel® Tera-scale Computing Research Program  The Intel® Tera-scale Computing Research Program is a worldwide effort to advance computing technology for the next decade  By scaling multi-core architectures to 10s to 100s of cores and embracing a shift to parallel programming, their aim is to improve performance, increase energy-efficiency.  Their vision is to create platforms capable performing of trillions of calculations per second (teraflops) on trillions of bytes of data (terabytes).  Their vision is to create platforms capable performing of trillions of calculations per second (teraflops) on trillions of bytes of data (terabytes).

Intel® Tera-scale Computing Research Program   Not only investigating the technologies necessary for Intel to build processors with tens or even hundreds of cores in the next 5-10 years, but also the platforms and software around those processors..  There are more than 100 projects in this program being carried out by Intel researchers in labs around the world.

Intel’s Teraflops Research Chip  One of these projects is Intel’s Teraflops Research Chip. This chip is Intel’s first silicon tera-scale research prototype.  It is the first programmable chip to deliver more than one trillion mathematical calculations persecond (1 Teraflops) of performance while consuming very little power.

Intel’s Teraflops Research Chip

A Historical Perspective, ASCI Red  1996 : First Teraflops Supercomputer developed by Intel  104 cabinets, over 2500sq feet.  Almost Pentium Pro Processors  Consumed 500kw

 100 million transistors  275mm2  Consumed 62 Watt Intel’s Teraflops Research Chip

Intel’s Teraflops Research Chip Performance

Innovations on Intel’s Teraflops Research Chip  Rapid design – The tiled-design approach allows designers to use smaller cores that can easily be repeated across the chip. A single-core chip of this size (100 million transistors) would take roughly twice as long and twice as many people to design.  Network on a chip - In addition to the compute element, each core contains a 5-port message passing router. These are connected in a 2D mesh network that implement message-passing. This mesh interconnect scheme could prove much more scalable than today’s multi-core chip interconnects, allowing for better ommunications between the cores and delivering more processor performance..  Fine-grain power management - The individual compute engines and data routers in each core can be activated or put to sleep based on the performance required by the application a person is running

Summary  Emerging applications will demand teraflop performance  Intel is developing technologies to enable Tera-scale computing  Intel’s terascale architecture contributes multicore architectures a lot.  It seems that product with Tera-scale processors is coming to the market in a few years.

References*  An 80-Tile Sub-100-W TeraFLOPS Processor in 65-nm CMOS, Vangal, S.R.;Solid-State Circuits, IEEE Journal of Volume 43, Issue1, Jan.2008 Page(s):29 – 41  An 80-Tile 1.28TFLOPS Network-on-Chip in 65nm CMOS Vangal, S; Solid-State Circuits Conference, ISSCC Digest of Technical Papers. IEEE International Feb Page(s):98 – 589  Programming the Intel 80-core network-on-a-chip terascale processor, G. Mattson ;Conference on High Performance Networking and Computing archive Proceedings of the 2008 ACM/IEEE conference on Supercomputing - Volume 00    IDF 2006: Terascale Processing Brings 80 Cores to your Desktop, Ryan Shrout,  An Overview of Intel's Teraflops Research Chip, Nathan Kirsch,