Development of the readout electronics in Lund for the ILD TPC Vincent Hedberg, Leif Jönsson, Anders Oskarsson, Björn Lundberg, Ulf Mjörnmark, Lennart Österman Phys. Dept., Lund Univ. in collaboration with the CERN group Outline of the talk: ●The present readout system - Status - Some results ●The future SALTRO16 based system - General considerations - Status of electronics development Carrier Board MCM-board Board Controller and serial readout LV-system

The present readout system Front End Cards:: 8 ALTRO ADC chips (ALICE) 8 PCA16 charge sensitive preamplifiers programmable w.r.t.shaping time (30, 60, 90, 120 ns) gain (12, 15, 19, 24 mV/fC) decay time (continuous) polarity Backplane with parallel bus readout RCU (Readout Control Unit)

Note: All tests of the performance of Micro Pattern Gas Detectors can be carried out with the present system! Physical size of the FEC: 19 x 17 cm 2 Number of channels /FEC: 128 Status: 64 (partly) damaged PCA16 chips on 30 FEC:s have been replaced and tested. Number of FEC‘s: ~ 80 Total number of channels: ~ Pad plane: Number of pads/module: 5152 Pad size: ~1.1 x 5.26 mm 2

Proof of principle Show that the required space resolution could be obtained Measurements in 1 T magnetic field with the Japanese GEM modules Sampling frequency 20 MHz Left: The fitted line crosses the y-axis at mm 2 which corresponds to an intrinsic resolution of  y (0) = 59.1 ± 0.4  m. Right; Extrapolating the fitted line to half the drift length of the final TPC gives  z =346 ± 9  m, which is well below the desired resolution of 500  m. An extrapolation to the full drift length (2.15 m) gives 446 ± 9  m, still below the goal resolution.

The future SALTRO16 based readout system Reduce the size of the electronics to match the size of pads that we are aiming for, i.e. 1 x 6 mm 2 for the SALTRO16 system. SALTRO16: integrates the analogue and digital signal processing into one chip. The backframe reduces the available area for electronics but not for pads. The space needed for HV-supply and cooling has to be taken into account. Status of the SALTRO16 chip: A small number of chips have been characterized at CERN and found to meet the design specifications. Around 10 packaged chips will be delivered to Lund for tests. Another 210 naked chips will be provided by CERN as a contribution to the LCTPC collaboration Additional 400 naked chips has been purchased by KEK and Saga University. If we assume 90% yield this corresponds to almost 9000 channels in total All chips are ready to be delivered to Lund from CERN. The chips are going to be mounted on small carrier boards.

Carrier board Why a carrier board?Standard packagings too big (chip not made for bump bonding in minimal BGA package) Special packagings too expensive Requirement:As small as possible  smaller pads The size of the die:Is the design size = physical size??? Design size: 5.25 x 8 mm 2 Physical size: Nobody can give an exact answer to this Best estimate: 6.04 x 8.71 mm 2 Further considerations:The thickness of the die is 225  m Bonding wires need minimum 250  m Additional space for soldering pads and passive components Final size of carrier board: 8.9 x 12 mm 2 Thickness:6 layers with blind vias gives a total thickness of 0.5 mm Mounting of chipGlued with conductive glue for grounding purpose Status:Design ready, waiting for bid

Test measurements of the SALTRO16 chip in Lund Packaged chips: Test board and the necessary firmware will be provided by CERN These tests enable us to repeat the measurements of CERN and verify their results. Good preparation for the selection measurements later Values and variations of parameters will determine what is acceptable for selecting a chip as good Naked chips: Chips on carrier boards makes handling and tests simpler/safer. Measurements need an adaptor board with the same size and pin structure as the pakaged chips in order to fit into the socket of the CERN test board. On the opposite side the adaptor board needs a socket with BGA foot print to provide connection to the carrier board. The selection procedure will be based on the measurement of some specific parameters

Multi Chip Module Status: The design is close to being ready. The carrier- and MCM-boards will be equipped with dummy components to make sure that the soldering procedure is adequate and to allow the company to test and optimize the soldering procedure. These dummy boards may also be used to test the cooling system. Four carrier boards are mounted on each side of the MCM giving a total of 8 x 16 = 128 channels i.e. the same as one FEC. In order not to increase the size of the MCM we had to remove one shift register which affects the choice of decay times such that they can no longer be chosen individually for each chip but will be the same for all chips on an MCM. Is the cooling sufficient to run without power pulsing? The board still needs a temp. sensor which allows for emergency shutdown

The organization of the MCM boards on a module 27 MCM boards  3456 channels = pads compared to 5152/module in the present system. Assuming the same pad width, the pad length will increase by ~ 50% from 5.26 mm to 7.84 mm. Open questions: Is the remaining area sufficient for HV-connectors? Is the layout compatible with the design of the cooling system? Available space below MCM-boards: Height of connector (3 mm?) mm (chip) –0.5 mm (carrier board) – space for bonding wires – epoxy protection layer – glue – soldering. Temp. Sensor 1.45 mm high.

Board Controller Status: planning phase

Organization of the electronics boards Possible solution: Short kapton cables between the MCM-board and the Board Controller Needs some mechanical support Preferred solution: Small right angle connectors, which we have not yet found

The full assembly Advantages: The low voltage system not so clumsy, thinner and fewer cables. Disadvantage: Little flexibility in rearranging the electronics boards

ALICE EMCal SRU solution uses existing FEC (including board controller) with ALTRO Bus readout. Modified BC firmware to send all data serially on one output channel at 40Mbit per sec. (sufficient for EMCal) FEC with 4 ALTROs Plug in card with lvds drivers and serial connector 8 leads Communicates to DAQ-like RCU Easy and fast option for the initial phase. BC slow but needs small firmware modifications (basically the serial ctrl of preamp/shaper) More advanced: new BC with serial Gbit output. More firmware development. Better for future. We have flexibility since BC is on separate small card Serial Readout

Alternative solution Advantage: Less space limited (space for noise protection components) Allows for smaller pad size (  4.4 mm 2 /channel) Simpler and more efficient cooling Right angel connectors available (same as for present system)

Summary  Present system ready for data taking in 2012 with up to channels  Saltro16 chips ready to be shipped from CERN to Lund  Design of carrier board ready, needs procurement  Design of MCM-board close to being ready, needs decision on horizontal/vertical mounting  Proposal for Board controller with serial readout  Ideas on a simplified LV-system