Practical Session 11 Computer Architecture and Assembly Language Input &Output (I/O)

Operating system CPU-Memory-I/O Architecture Input / Output (I/O) devices Input / Output (I/O) devices are used to interact with “outside world” mouse, screen, disks, printer … CPU I/O module / I/O driver I/O device I/O controller

I/O Controller Example: character output Check status register of I/O controller e.g. busy, idle, offline Put data into data in register Put command into command register e.g. “send the character in data register to printer” Data in Data out I/O Controller has 3 internal registers Typically I/O Controller has 3 internal registers: – Data register – Status register – Command register

Programmed I/O Software controls I/O operations – slow  – busy CPU wait  – simple Interrupt-driven I/O Device includes a signal to interrupt CPU Device includes a signal to interrupt CPU (interrupt is produced by hardware) When an interrupt occurs (and is accepted), a special routine executes to service the interrupt – no CPU busy wait Direct memory access (DMA) Direct memory access (DMA) I/O CPU transfer information to DMA controller (DMAC) location of data on device location of data in memory size of block to transfer direction of transfer When device is ready, DMAC takes control of the system buses DMA Controller

5 to DMA module controller controller I/O controller controller to DMA module controller I/O controller

I/O Ports I/O port is the address of I/O controller register Two kinds of mapping: Isolated I/O – separate address spaces – special commands for I/O 64 KB x86 provides 64 KB of isolated I/O address space in instruction is used to read data from I/O port: in register, port address (direct address) in register, DX (indirect address) out instruction is used to write data to I/O port: out port address, register (direct address) out DX, register (indirect address) register must be AL, AX, or EAX Two address spaces mov byte [0x60], ‘a’ Example: 0x60 ‘a’ mov AL, ‘a’ out 0x60, AL RAM 0x60 ‘a’ I/O controller data out register is not physical memory I/O ports is not physical memory, it is virtual mapping of I/O controllers’ registers and to their addresses I/O controlleraddress Screen device0x60 …… I/O ports mapping table

I/O Ports I/O port is the address of I/O controller register Two kinds of mapping: Memory mapped I/O – no special commands for I/O – use regular memory read/write commands mov byte [0x60], ‘a’ Example: 0x60 RAM 0x60 ‘a’ Screen device I/O controller data out register I/O controlleraddress Screen device0x60 …… mov byte [0x80], ‘b’ 0x80 ‘b’ I/O ports mapping table

Example – How to Write a Simple Keyboard Driver Use PA input port register at address 60h – PA7 = 0 if a key is pressed – PA7 = 1 if a key is released – PA0–PA6 = key scan code Use busy wait loop – wait until a key is pressed (i.e. until PA7 = 0) – read scan code of the key – wait until a key is released (i.e. until PA7 = 1) Pressing ESC key terminates the program PA0PA1PA2PA3PA4PA5PA6PA7

section.data ESC_KEY EQU 0x1B ; ASCII code for ESC key KB_DATA EQU 0x60 ; port PA section.text global _start _start: key_down_loop: ; loop until a key is pressed i.e., until PA7 = 0 in AL, KB_DATA; read keyboard status & scan code test AL, 0x80 ; PA7 = 0? (0x80= b ) jnz key_down_loop ; if not, loop back and AL,0x7F ; (0x7F= b ) – isolate scan code..translate scan code to ASCII code in AL.. cmp AL, ESC_KEY ; ESC key - terminate program je done key_up_loop:; loop until a key is released i.e., until PA7 = 1 in AL, KB_DATA ; read keyboard status & scan code test AL, 0x80; PA7 = 1? (0x80= b ) jz key_up_loop ; if not, loop back (busy wait) jmp key_down_loop done:..exit program.. Example – How to Write a Simple Keyboard Driver TEST instruction performs a bitwise AND on two operands. The flags SF, ZF, PF are modified while the result of AND is discarded.