Adiabatic Technique for Energy Efficient Logic Circuits Design

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Presentation transcript:

Adiabatic Technique for Energy Efficient Logic Circuits Design BY: M.Raj Lahari 12B41D5709

Why low power? Desirability of portable devices. Advent of hand held battery operated devices. Large power dissipation requires larger heat sinks hence increased area. Cost of providing power has resulted in significant interest in power reduction of non portable devices

Basics of Adiabatic Circuits: Conventional CMOS: When PFET is Switched ON, Energy from Source=CV2 Energy in Capacitor= ½CV2 Energy Lost = ½CV2 -> PFET Q=CV, E=CV2 Vin = 0 Q=CV, E=½CV2 When NFET is Switched, Energy Drained= ½CV2 Energy Lost = ½CV2 -> NFET A switching event always dissipates energy equal to signal energy, ½CV2

Basics of Adiabatic Circuits: Adiabatic Charging: The energy dissipation in Resistance R is Since Ediss depends upon R, so by reducing the on resistance of PMOS network the energy dissipation can be minimized.

Ediss also depends upon the charging time T, If T>> 2RC then energy dissipation will be smaller than the conventional CMOS . The energy stored at output can be retrieved by the reversing the current source direction during discharging process instead of dissipation in NMOS network. Hence adiabatic switching technique offers the less energy dissipation in PMOS network and reuses the stored energy in the output load capacitance by reversing the current source direction.

Proposed Adiabatic Circuits: Efficient Charge Recovery Logic (ECRL) Positive Feedback Adiabatic Logic (PFAL)

Efficient Charge Recovery Logic (ECRL)

Positive Feedback Adiabatic Logic (PFAL)

IMPACT OF PARAMETER VARIATIONS ON THE ENERGY CONSUMPTION Transition Frequency Variation Fig.11 Energy consumption per cycle versus frequency for an inverter at VDD = 2.5V and load capacitance = 20fF.

IMPACT OF PARAMETER VARIATIONS ON THE ENERGY CONSUMPTION Load Capacitance Variation

IMPACT OF PARAMETER VARIATIONS ON THE ENERGY CONSUMPTION Supply Voltage Variation

CONCLUSION less energy consumption in adiabatic logic families can be still achieved than CMOS logic over the wide range of parameter variations. PFAL shows better energy savings than ECRL at the high frequency and high load capacitance. Hence adiabatic logic families can be used for low power application over the wide range of parameter variations.

References W. C. Athas, L.J. Svensson, J.G. Koller, N. Tzartzanis, and E. Chou, “Low power digital systems based on adiabatic-switching principles,” IEEE Trans. VLSI Systems, vol. 2, no. 4, pp. 398-407, Dec. 1994. J. S. Denker, “A review of adiabatic computing,” in IEEE Symp. on Low Power Electronics, pp. 94-97, 1994. A. P. Chandrakasan, S. Sheng, and R. W. Brodersen, “Low-power CMOS digital design,’’ IEEE J. Solid-State Circ., vol. 27, no. 4, pp. 473-484, Apr. 1992. A. G. Dickinson and J. S. Denker, “Adiabatic dynamic logic,” IEEE J. Solid-State Circuits, vol. 30, pp. 311–315, Mar. 1995. J. G. Koller and W. C. Athas, “Adiabatic switching, low energy computing, and the physics of storing and erasing information,” IEEE Press, in Pmc. Workshop on Physics and Computation, PhysCmp ’92. oct. 1992.

Thank You