KAIST Power Electronics Lab, Dept. of EE., KAIST LG Semicon Hall (N24) 4102, 373-1, Guseong-dong, Yuseong-gu, Daejeon , Korea. TEL: , FAX: , Flyback converter

2 KAIST Power Electronics Lab., KPEL Analysis of flyback Contents Experiment Design procedure Conclusion Introduction

3 KAIST Power Electronics Lab., KPEL Part 1. Introduction

4 KAIST Power Electronics Lab., KPEL Spec V in,ac = 85V ~ 264V V out : V o1 = 5V, I o1 = 4A V o2 = 14V, I o2 = 3A f s = 67kHz Introduction Design AC / DC multi output flyback converter Advantage Smaller size Fewer component Disadvantage Hard switching low efficiency High switch voltage stress

5 KAIST Power Electronics Lab., KPEL Introduction CCM - DCM CCM operation DCM operation Output voltage When load change, multi-output voltage regulation of CCM is better

6 KAIST Power Electronics Lab., KPEL Part 2. Analysis of flyback

7 KAIST Power Electronics Lab., KPEL Analysis of flyback Circuit diagram

8 KAIST Power Electronics Lab., KPEL waveform Analysis of flyback

9 KAIST Power Electronics Lab., KPEL waveform Analysis of flyback

10 KAIST Power Electronics Lab., KPEL waveform Analysis of flyback

11 KAIST Power Electronics Lab., KPEL waveform Analysis of flyback

12 KAIST Power Electronics Lab., KPEL waveform Analysis of flyback Energy transfer Until switch is ‘ON’

13 KAIST Power Electronics Lab., KPEL waveform Analysis of flyback

14 KAIST Power Electronics Lab., KPEL Part 3. Design prosedure

15 KAIST Power Electronics Lab., KPEL DC link capacitor Design of flyback Total output power = 62W Assumed efficiency of 85%, total input power = 73W DC link capacitor as 2~3uF per watt So DC link capacitor is selected 164uF Minimum input voltage

16 KAIST Power Electronics Lab., KPEL Minimum voltage Design of flyback Charging E = Discharging E

17 KAIST Power Electronics Lab., KPEL Design of flyback Turn ratio and maximum duty Minimum duty

18 KAIST Power Electronics Lab., KPEL Design of flyback

19 KAIST Power Electronics Lab., KPEL Design of flyback Core selection We choose PQ3220S core (A p = 13736mm 4, A e = 170mm 2, A W = 80.8mm 2 ) Minimum turn

20 KAIST Power Electronics Lab., KPEL Wire and turn selection Design of flyback Primary wire : 1 strand of ritz wire (0.1Φ – 30strands) Secondary 2 wire : 2 strands of ritz wire (0.1Φ – 40strands) Secondary 1 wire : 3 strands of ritz wire (0.1Φ – 30strands) J = 7.43A/ mm 2 J = 7.87A/ mm 2 J = 7.15A/ mm 2

21 KAIST Power Electronics Lab., KPEL Secondary diode selection Design of flyback Voltage of diode Current of diode TYPEPart Namevoltage(V)Current (A)V F (V) SCHOTTKYB30H80G SCHOTTKYSTPS30120CT Select schottky diodes Output capacitor selection

22 KAIST Power Electronics Lab., KPEL Design of flyback Snubber design TYPEPart Namevoltage(V)Current (A)R ds_on (Ω) NMOSIPA60R385CP

23 KAIST Power Electronics Lab., KPEL Part 4. experiment

24 KAIST Power Electronics Lab., KPEL Full load at 85V AC Full load at 264V AC Experiment result

25 KAIST Power Electronics Lab., KPEL Full load at 85V AC Full load at 264V AC Experiment result

26 KAIST Power Electronics Lab., KPEL CCM - DCM Conclusion CCM to DCM at 20% load

27 KAIST Power Electronics Lab., KPEL Conclusion 20% load40% load60% load80% load100% load Master current(A) Master voltage(V) Slave current(A) Slave voltage(V) Efficiency(%) % load40% load60% load80% load100% load Master current(A) Master voltage(V) Slave current(A) Slave voltage(V) Efficiency(%)

28 KAIST Power Electronics Lab., KPEL Power efficiency conclusion Calculate some loss

29 KAIST Power Electronics Lab., KPEL Part 5. conclusion

30 KAIST Power Electronics Lab., KPEL Conclusion Understand flyback converter Make closed loop circuit, gate driver and controller(TL 494) on the board Maximum efficiency is 87.78%

31 KAIST Power Electronics Lab., KPEL