1 CE 454 Computer Architecture Lecture 6 Ahmed Ezzat The Digital Logic, Ch-3.3, 3.4,

CE 454Ahmed Ezzat 2 Outline Memory – Latches – Flip-Flops – Registers – Memory Organization – RAMs and ROMs CPU and Buses – CPU Chips – Computer Buses – Bus Width – Bus Clocking – Bus Arbitration – Drawing Conventions Reading Assignment: Ch 3.5, 3.6

CE 454Ahmed Ezzat 3 Memory So far we saw only memory-less digital functions But we need to store the program, the data and the intermediate values used by an application running on a processor We know from ISA that there are registers and memory – where does data in “ADD R4, R6” reside? – What are these R4, R6 “registers”? – how do they work? How are they constructed? – will explain using gates in a way similar to combinational logic

CE 454Ahmed Ezzat 4 Memory Are made from sequential circuits – But require feedback: new “state” = F(current state, inputs) Require timing to be taken into account – will assume non-zero gate delay – will introduce the concept of “clock” New state: a boolean function which depends on – inputs from  T earlier – state from  T earlier

CE 454Ahmed Ezzat 5 Memory: Set-Reset (SR) Latches A Set-Reset (SR) Latch – Q and Q’ are fed back as inputs making it sequential A bi-stable circuit that stores binary values – Q=1, Q=0 is a “1” state – Q=0, Q=1 is a “0” state Can only be in one of these states – output change requires S and R to be applied – if S=R=0 then Q remains unchanged — —

CE 454Ahmed Ezzat 6 Memory: Set-Reset (SR) Latches S=R=1 leads to an unstable state. The output Q may “oscillate” before settling down to either 1 or 0. if S=R=0 then Q remains unchanged

CE 454Ahmed Ezzat 7 Memory: Set-Reset (SR) Latches Summary SR inputs and the resulting state – SR = 10  Q=1, Q’=0 (“1” state) when SR goes to 00 state remains the same: Q=1, Q’=0 – SR = 01  Q=0, Q’=1 (“0” state) when SR goes to 00 state remains the same: Q=0, Q’=1 – SR = 00 then Q remains unchanged – SR = 11 is not allowed electronically unstable state... Can only be in a state such that – Q’ = NOT Q – output change requires either S=1 or R=1 to be applied Once input is removed the latch “remembers” – stays in the same state

CE 454Ahmed Ezzat 8 Memory: Set-Reset (SR) Latches Time Diagram In an SR latch output Q follows input changes Note the delay (lag) between input changes and output changes Q Q S R tt tt 2t2t 2t2t

CE 454Ahmed Ezzat 9 Memory: Set-Reset (SR) Latches Problems with SR Latches Combinational functions take time to settle – output may vary for a while before going to correct value If S,R change then Q will change – with many levels of gates the change propagates for a while may not “settle” in time We assume that  T is the delay of a NOR gate How long we need to wait for R or S to be stable at 1 so as – Q is stable at 0 – Q is stable at 1, respectively

CE 454Ahmed Ezzat 10 Memory: Set-Reset (SR) Latches Problems with SR Latches How to make sure changes to registers occur – when desired; once per cycle ! Modify the latch – incorporate a clock signal as one of the inputs Will design a computer with many latches How to make sure things happen when required? Consider a basic arithmetic operation – Take data from 2 registers – Run through the ALU – Store to another register – Need to make sure these three steps occur at the right time Solution: generate and distribute a special signal called clock – keeps time: acts as a conductor for an orchestra or a drummer in a band – To ensure change occur: when desired only once per clock cycle

CE 454Ahmed Ezzat 11 Memory: Clocked SR Latches Q only changes when the Clock is a 1. If Clock is 0, neither S or R reach the NOR gates.

CE 454Ahmed Ezzat 12 Memory: Clocked SR Latches Still We have Problems Undefined state (S=R=1) Latency of Inputs/clock – Inputs can change as long as clock is (still) high One half of the clock cycle – That’s too long A solution - The D-latch Then we can play with duty cycle to limit when high – percent of clock cycle that is “1” – generate a very narrow “1” clock pulse but it is hard, especially at 2 GigaHertz – “sample” input (D) only when clock is “1”

CE 454Ahmed Ezzat 13 Memory: Clocked D Latches Avoid S=R=1; only one input If D is a 1 when the clock becomes 1, the circuit will remember the value 1 (Q=1). If D is a 0 when the clock becomes 1, the circuit will remember the value 0 (Q=0).

CE 454Ahmed Ezzat 14 Memory: Clocked D Latches Narrow Clock Pulse (~5 nsec)

CE 454Ahmed Ezzat 15 Memory: Flip-Flop (Master/Slave) Q D C

CE 454Ahmed Ezzat 16 Memory: D Latches vs Flip-Flop (a): is a D latch whose state is loaded when clock is 1 (b): is a D latch whose state is loaded when clock is 0 (c): is a F/F change state on the rising edge of the clock pulse (d): is a F/F change state on the falling edge of the clock pulse Some latches and F/Fs provide also Q as output, and Set and Reset as additional inputs 

CE 454Ahmed Ezzat 17 Memory: Registers 8-Bit Register We can use 8 D Latches to create an 8 bit memory. We have 8 inputs that we want to store, all are written at the same time. All 8 latches use the same clock. clock  D Latch D0D0 D1D1 D3D3 D4D4 D5D5 D6D6 D2D2 D7D7 Q0Q0 Q1Q1 Q3Q3 Q4Q4 Q5Q5 Q6Q6 Q2Q2 Q7Q7

CE 454Ahmed Ezzat 18 Memory: Registers Register Notations Notationally registers are referred to as one unit instead of addressing each storage element individually. A Data_in[7:0] Data_out[7:0] Clock

CE 454Ahmed Ezzat 19 Memory: Memory Organization Random Access Memory (RAM) Access time – from address to data out Constant access time – independent of address – unlike tape or disk Semiconductor memory: – RAM – ROM Many bits on one IC Each bit is a “latch” Depending on type get – Static (SRAM) – Dynamic (DRAM) Speed Capacity Cost Speed, cost, size relationship:

CE 454Ahmed Ezzat 20 Memory: Memory Organization Logic diagram for 4 x 3 Memory 4 rows of clocked D latches, each is a 3 bits. 3 input data lines (I 0.. I 2 ) 2 input address lines (A 0, A 1 ) 3 output lines (Q 1.. Q 2 ) CS (clock) line RD (READ/Write) line OE (output enable) line For Read, input lines are not used. For Write, output lines are not used

CE 454Ahmed Ezzat 21 Memory: Memory Organization Noninverting Buffer A tri-state device: 0, 1, none Output equal input (short circuit), or none (open circuit) A side effect it functions as amplifier, I.e., in addition to its switching properties Inverting Buffer Sam as noninverting, with short circuit when control input is low (amplifier effect)

CE 454Ahmed Ezzat 22 Memory: Memory Chips Memory IC is typically organized as a cell matrix – NxN At each position is a single cell To get wider output - replicate the matrix – 128Mbx8b IC may have 8 blocks (individual NxN matrices) Memory is built out of multiple chips – 256MB DIMM may have Mx8b ICs Eight are read (written) at once delivering 64b of data

CE 454Ahmed Ezzat 23 Memory: RAMs and ROMs RAMs –Static – F/F –Dynamic – transistor + capacitor –Synchronous ROMs –PROM –EPROM –EEPROM –Flash EPROM – disk replacement potential

CE 454Ahmed Ezzat 24 CPU CHIPs and Buses: CPU Chips From an internal (to the computer system) point of view, I/O is functionally similar to memory There are two operations read/write I/O module may control more than one device. The interfaces to each external devices is referred to as port, and each port is given a unique address External data path for input output data with external devices I/O module may be able to send interrupt signals to the CPU

CE 454Ahmed Ezzat 25 CPU CHIPs and Buses: Computer Buses Memory to processor Processor to memory I/O to processor Processor to I/O I/O to and from Memory (DMA)

CE 454Ahmed Ezzat 26 CPU CHIPs and Buses: Computer Buses Data Exchange Memory to processor Processor to memory I/O to processor Processor to I/O I/O to and from Memory (DMA)

CE 454Ahmed Ezzat 27 CPU CHIPs and Buses: Computer Buses Binary 0 Binary 1 Leading edge Trailing edge Time gap Time Signal as a function of time All lines 0 Not all lines necessarily 0All lines 0 Group of lines Cause and effect dependency Clock Timing Diagram

CE 454Ahmed Ezzat 28 CPU CHIPs and Buses: Computer Buses Bus Types Dedicated – Physical: Connected to a subset of modules – Functional: Data bus, Address Bus Multiplexed: Time multiplexing Address Data Time

CE 454Ahmed Ezzat 29 CPU CHIPs and Buses: Computer Buses Bus Configuration

CE 454Ahmed Ezzat 30 CPU CHIPs and Buses: Bus Width Address lines – Increases over time Data lines – Decrease bus cycle (bus skew) – Increase data lines Multiplexed: to allow very wide buses

CE 454Ahmed Ezzat 31 CPU CHIPs and Buses: Bus Clocking Synchronous Buses

CE 454Ahmed Ezzat 32 CPU CHIPs and Buses: Bus Clocking Asynchronous Buses

CE 454Ahmed Ezzat 33 CPU CHIPs and Buses: Bus Arbitration One device is designated as master, which may initiate a data transfer with some other device (slave) More than one module (e.g. CPU and DMA controller ) may need control of the bus Only one module may control bus at one time Needs some form of arbitration l Centralised Arbitration  Single hardware device controlling bus access (Bus Controller or Arbiter)  May be a separate module or part of CPU or separate l Distributed Arbitration  Each module may claim the bus  Control logic on all modules

CE 454Ahmed Ezzat 34 CPU CHIPs and Buses: Bus Arbitration Centralized

CE 454Ahmed Ezzat 35 CPU CHIPs and Buses: Bus Arbitration Decentralized

CE 454Ahmed Ezzat 36 CPU CHIPs and Buses Drawing Conventions Thick lines are buses - multiple bits wide Dotted line is clock Dashed lines are control signals

CE 454Ahmed Ezzat 37

CE 454Ahmed Ezzat 38 PCI Bus Peripheral Component Interconnect Start development 1990 Became standard 1995 Used in: – Sun Workstations – Apple Macintosh – Wintel PCs – Compaq Alpha Server The same peripheral I/O cards may be plugged into many different computers