Development of novel n + -in-p Silicon Planar Pixel Sensors for HL-LHC Y. Unno a, J. Idarraga 1, S. Mitsui a, R. Hori a, R. Nagai g, O. Jinnouchi g, A. Lounis 1, Y. Takahashi h, K. Hara h, S. Kamada b, K. Yamamura b, A. Ishida b, M. Ishihara b, T. Inuzuka b, Y. Ikegami a, T. Kondo a, Y. Takubo a, S. Terada a, J. Tojo a, R. Takashima c, I. Nakano d, K. Hanagaki e, N. Kimura i, K. Yorita i a High Energy Accelerator Research Organization (KEK) and The Graduate University for Advanced Studies (SOKENDAI) b Hamamatsu Photonics K.K. c Department of Education, Kyoto University of Education d Department of Physics, Okayama Univeristy e Department of Physics, Osaka University f Universite de Paris-Sud 11 g Department of Physics, Tokyo Institute of Technology h Institute of Pure and Applied Sciences, Univeristy of Tsukuba i Research Institute for Science and Engineering, Waseda University Y.Unno, HSTD8, 2011/12/61

Introduction Planar pixel sensor aiming for very high radiation environment, such as high-luminosity LHC – – a few x n eq /cm 2 n-in-p benefits – No type inversion after irradiation Single side lithographic process – Low cost – Readout from n+ of p-n junction Possible partial depletion operation – In all circumstances Readout in higher electric field – Stronger induction current Collecting electrons – Faster carrier, less trapping n-in-p strips were reported in the last symposium (HSTD7) – Y. Unno et al., Nucl. Instr. Meth. A 636, Supplement, 21 April 2011, Pages S24-S30, and other 3 papers in the issue. Y.Unno, HSTD8, 2011/12/62

n-in-p pixel issues n-in-p issues – Isolation of n+ pixels – HV protection at the diced edge Issues in planar pixel sensor in general – HV operation capability Up to 1000 V, e.g., to cope with radiation damage in bulk – Material reduction Thin sensor – Inefficient area due to “bias” structure required for testing all pixels, with I-V performance, e.g. – Bump bonding limited number of vendors Content of the talk – Pixel structures Biasing x Isolation Thin sensor – HV protection – Bump-bonding Y.Unno, HSTD8, 2011/12/63

PTLA PolySi Bias rail Biasing Scheme Isolation scheme Novel n-in-p HPK Pixel Sensors n-in-p 6-in. wafer process in HPK – ATLAS FE-I3 and FE-I4 pixel sensors – Biasing: Punth-thru (PT) dot at 4-corner or PolySi resister – Isolation: p-stop (common, individual) or p- spray – “Bias rail” is a metal over insulator, no implant underneath. No electrode in the silicon, other than the bias “dot” Thinning – Finishing 320 µm wafer process first – Thinning the wafers to 150 µm – Completing the backside Y.Unno, HSTD8, 2011/12/64 HPK n-in-p 6-in. wafer FE-I4 2-chip pixels FE-I4 1-chip pixels FE-I3 1-chip pixels FE-I3 4-chip pixels FE-I3 (~1cm □ ) FE-I4 (~2cm □ )

1 µA FE-I4 1-chip, FE-I3 4-chip FE-I4 2-chip FE-I3 1-chip Thin n-in-p HPK Pixel Sensors I-V performance (before UBM and dicing) – All (-most) were good up to 1000 V – p-spray sensors break around 900 V, still good After bump-bonding – 4 out of 4 were all good up to 1000 V 16 wafers are processed – 150 µm thick 4 wafers were sent for UBM+Bumpbonding. Measured data of the 3 wafers of p- stop: – 18 FE-I4 1-chips – 18 FE-I4 2 –chips – 21 FE-I3 1-chips – 9 FE-I3 4-chips Y.Unno, HSTD8, 2011/12/65

p-stop common, Poly-Si p-stop individual, PTLA #5# p-stop individual, Poly-Sip-stop common, Poly-Si #3 #4#4 [μm] [μm][μm] 1 2D efficiency map of one pixel, non-irrad, at 150 V bias voltage black : avg. non-irradiated red : avg. irradiated (2x10 15 ) Bias voltage [V] Q [e] (Arbitrary unit) Bias voltage dependence of collected charges Note: independent charge calibration for non-irradiated and irradiated samples. Before/After irradiation Results from test beams – 2x10 15 n eq /cm 2 – See the poster by R. Nagai et al. Slim edge, multi guard – 5x10 12 – 5x10 15 n eq /cm 2 – See the poster by S. Mitsui et al. Y.Unno, HSTD8, 2011/12/66 Arbitrary unit Shallow incident angle analysis No charge mult. yet… 99.2% 99.8% 94.1% Depth (mm)

HV protection – Low-tech solutions Real pixel sensor (FE-I3) + dummy chip (Al traces) – bump-bonded Three types of encapsulation – Encapsulation material – Silicone adhesive (soft) – No encapsulation (#1), X-points (#2), full line (#3) Y.Unno, HSTD8, 2011/12/67 Weak cross points #1: No encapsulation #2: Encapsulation of x-points #3: Full line encapsulation 1. Encapsulation

Encapsulation – Spark test Spark occurs – ~500 V at X-points without protection good info. – ~700 V at Al-traces facing to the sensor edge No open/no passivated trace in the real FE-I4 chips (?) – No spark up to 1000 V with full encapsulation We have at least a candidate to protect the edge. Y.Unno, HSTD8, 2011/12/68 Spark location #1: Spark location – X-points ~500 V #2: Spark location – Al trace ~690 V #3: No spark up to 1000 V

Encapsulation – FE-I4’s testbeam Post-process application – Silicon adhesive – Both non-irradiated and irradiated single chip modules (SCM) – successfully operated up to 1000 V in the testbeam Y.Unno, HSTD8, 2011/12/69

HV protection – 2. Parylene coating Parylene coating – Two FE-I3 SCMs After wire-bonding Covering all over Parylene C, ~3 µm – Softer Parylene-N might be better (?) – I-V measurement Shorted ~700 V Consistent with known shorts in the single chip card Y.Unno, HSTD8, 2011/12/610 Parylene coating (C: ~3 µm) 1.1x MeV n eq /cm °C, No LV power FE-I4 single chip cardCoated area FE-I3 module

Bump-bonding at HPK IZM – Well-established through current pixel detectors at LHC – PbSn solder bumps – old fashioned HPK dummy chips + IZM UBM+PbSn bumps FE-I3 HPK sensor + FE-I3 chips (with IZM PbSn bumps) – Testbeam in Oct – Irradiation in Feb – SnAg (Pb-free) bumps (by HPK) - current industry standard HPK dummy chips + HPK UBM + SnAg bumps 320 µm and 150 µm FE-I3 and FE-I4 types – Singles and “4-chip”s – Irradiation and testbeams in 2011 Establishing the technology at HPK – Benefits in doing at the sensor vendor Faster and invaluable internal feedback – both in the bump-bonding and sensor fabrication Y.Unno, HSTD8, 2011/12/611

FE-I4 FE-I3 PbSn Bump-bonding at HPK Al-pattern with bumps – Pb (PbSn) and Pb-free (SnAg) solder – FE-I3 and FE-I4 pattern – Single chips Multi-chips next Results – Good peel strength – Good yield of bump connection – ~0.14 Ω/bump resistance 12Y.Unno, HSTD8, 2011/12/6 Number of bumps (FE-I4 type) Resistance (Ω) FE-I4 Dummy FC Resistance ~0.14 Ω/bump

SnAg Bumpbonding at HPK Latest achievement – FE-I4 single chip – 150 µm thickness both – ~0.28 Ω/bump 4-chip trials – with dummy sensor & chips – both 320 µm thick – Pb-free (SnAg) bumps Y.Unno, HSTD8, 2011/12/ µm thick 4-chip module FE-I4 single chip daisy-chain sample Integral Resistance (Ω) Resistance per 2-rows (Ω) Number of bumps

Thermal cycling Low (-40 °C) and High (+50 °C) Climate chambers, each with a large aluminum block for a thermal capacitor Samples were laid on an aluminum box. A pt100 resistor was also attached on a silicon piece. – Temperature of the pt100 was read out with a Keithley 2700 multimeter The aluminum box was placed on the aluminum block for 30 min. Transfer the sample box by hand 14 sample High temp. Climate Ch. Alumi block sample Low temp. Climate Ch. Alumi block Transfer Pt100 sample Alumi box Y.Unno, HSTD8, 2011/12/6

Temperature reading per 10 s Results of FE-I4 single chip dummies Temperature slope upward – First 30 s, first 1 min. averages – 54.09K/30s 、 73.43K/min Temperature slope downward – K/30s 、 K/min ~70 K/min thermal shock was achieved Consistent resistances before/after thermal cycling of 10 time – 1st-last pad resistance All 6 samples has survived. 15 ℃ h FEI-4Before (Ω)After (Ω) Y.Unno, HSTD8, 2011/12/6

Summary Thin FE-I3 and FE-I4 pixel sensors were successfully processed, with novel biasing and isolation schemes. FE-I4 thin pixel 1-chip SCMs, bump-bonded at IZM, were evaluated through a chain of testbeam, irradiation, and testbeam. Results for the biasing and isolation performance comparison are in hand. – Polysilicon biasing with common p-stop isolation performs best. Low-tech solution of HV protection has been tried out with – Parylene coating and encapsulation – Both were successfully preventing HV shorts, up to 1000 V. SnAg bump-bonding at HPK are being established. – Chip thickness of 150 µm and 320 µm – Dummies have survived after 10 time of thermal cycling with the temperature slope of ~70 K/min. Y.Unno, HSTD8, 2011/12/616

Backup Y.Unno, HSTD8, 2011/12/617

Features in HPK n-in-p Sensors Bias structures – Reducing less-efficient area – PTLA (a bias-dot in the 4-corner) – PolySilicon (encircling pixel implant) Isolation structures – p-stop (~4x10 12 cm -2 ) Common Individual – p-spray (~2x10 12 cm -2 ) “Bias rail” is a metal over insulator, no implant underneath No electrode in the silicon, other than the bias “dot” PTLA PolySi Bias rail Biasing Scheme Isolation scheme 18Y.Unno, HSTD8, 2011/12/6

HPK thin pixel sensor FE-I4 SCM’s 4 HPK thin sensors were bump-bonded at IZM. Delivered to Univ. Bonn and waiting for mounting to the boards. Characterization and testbeam – Initial characterization will be carried out at Bonn. – Further characterization in Japan, in June – Looking forward to the testbeam at CERN in July (and Sep.) – Irradiation (at Karlsruhe(?)) at a time of July-Sep.(?) Y.Unno, HSTD8, 2011/12/619 PriorityWafer No.Chip No.typeUBMI-V 11937PolySi-commonOK 21837PolySi-commonOK 31735PTLA-individualOK 41738PolySi-individualOK 53339PolySi-PsprayOK 61835PTLA-individualOK 71838Poly-Si individualOK 81935PTLA-individualOK 91938Poly-Si individualOK PolySi-commonOK400 V