Yuxi Liu The Chinese University of Hong Kong Circuit Timing Problem Driven Optimization

Outline Timing problem Background Optimization for hardware cost Optimization for high performance

Reliability Problem Ever-increasing uncertainties with technology scaling Static and dynamic variations Environmental fluctuations Less effective manufacturing test Transistor feature size continuously shrinking 22nm transistor by 2011, 14nm followed Circuit reliability problem becomes more severe!

Timing Error Problem Timing speculation Allow infrequent timing errors Online detection and recovery Better throughput, higher energy-efficiency Representative technique: Razor “Ernst et al. [MICRO 2003]” Conventional solution: embed design guardband Guarantee timing correctness Diminish benefits of scaling More vulnerable to timing problems Delay uncertainty

Razor FF & Timing Speculation Error_L Error comparator RAZOR FF clk_del Main Flip-Flop clk Shadow Latch Q1 D1 0 1 Double latch the input data Detect the error when latched data disagree Correct when error detected: flush and replay

Cost for Timing Speculation clock clock_del t delay t hold Min. path delay Min. Path Delay > t delay + t hold intended pathshort path Hardware cost Throughput loss from error rate Clock cycle T, Error penalty r, Working correctly rate P

Optimization for Hardware Cost Linear programming approach is not scalable Heuristic method Focus on suspicious FFs and the related FFs FF Traditional retiming: reduce the maximum path delay Our target: reduce the number of critical paths Reduce number of SFFs

Optimization for Throughput Throughput is determined by timing error rate Reduce error rate 1-P can increase throughput Reduce error rate Reduce the sensitization probability of critical paths Shorten critical paths with high sensitization probability Consideration during logic synthesis is promising Circuit structure is expected to be changed More flexibility comparing with post-synthesis methods

Timing Optimization For traditional timing optimization Minimize worst-case path delay Balance the delay among different paths Optimization for timing error probability Aware of error rate information during process Optimization is performed on each super-gate Associative transform: a(bc)=(ab)c=(ac)b Reorder all fanins of the supergates

b c a Timing Optimization Optimization performed at every super-gate Not balance the delay of different paths Locate fanin with paths more critical closer to output Shorten all critical paths through this fanin Lengthen paths which are less critical Consideration for technology mapping More accurate timing information

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