1 - CPRE 583 (Reconfigurable Computing): VHDL overview 1 Iowa State University (Ames) CPRE 583 Reconfigurable Computing Lecture 2: 8/26/2011 (VHDL Overview 1 ) Instructor: Dr. Phillip Jones Reconfigurable Computing Laboratory Iowa State University Ames, Iowa, USA

2 - CPRE 583 (Reconfigurable Computing): VHDL overview 1 Iowa State University (Ames) VHDL review 1 –Highly recommend VHDL tutorial 120 pages with a LOT of examples –Quick reference (quick ref) –Some links other VHDL tutorials HW 1 overview Overview

3 - CPRE 583 (Reconfigurable Computing): VHDL overview 1 Iowa State University (Ames) VHDL basics VHDL: (V)HSIC (H)ardware (D)escription (L)anguage –VHSIC: (V)ery (H)igh (S)peed (I)ntegrated (C)ircuit It is NOT a programming language!!! It is a Hardware Description Language (HDL) Conceptually VERY different form C,C++

4 - CPRE 583 (Reconfigurable Computing): VHDL overview 1 Iowa State University (Ames) Some Key Differences from C C is inherently sequential (serial), one statement executed at a time VHDL is inherently concurrent (parallel), many statements executed at a time

5 - CPRE 583 (Reconfigurable Computing): VHDL overview 1 Iowa State University (Ames) Some Key Differences from C C example VHDL example A = B + C X = Y + Z Ans = A + X Initially: A,B,C,X,Y,Z,Ans =1 A <= B + C X <= Y + Z Ans <= A + X Current Values: A = 1 B = 1 C = 1 X = 1 Y = 1 Z = 1 Ans = 1 Current Values: A = 1 B = 1 C = 1 X = 1 Y = 1 Z = 1 Ans = 1

6 - CPRE 583 (Reconfigurable Computing): VHDL overview 1 Iowa State University (Ames) Some Key Differences from C C example VHDL example A = B + C X = Y + Z Ans = A + X Initially: A,B,C,X,Y,Z,Ans =1 A <= B + C X <= Y + Z Ans <= A + X Current Values: A = 2 B = 1 C = 1 X = 1 Y = 1 Z = 1 Ans = 1 Current Values: A = 1 B = 1 C = 1 X = 1 Y = 1 Z = 1 Ans = 1

7 - CPRE 583 (Reconfigurable Computing): VHDL overview 1 Iowa State University (Ames) Some Key Differences from C C example VHDL example A = B + C X = Y + Z Ans = A + X Initially: A,B,C,X,Y,Z,Ans =1 A <= B + C X <= Y + Z Ans <= A + X Current Values: A = 2 B = 1 C = 1 X = 2 Y = 1 Z = 1 Ans = 1 Current Values: A = 1 B = 1 C = 1 X = 1 Y = 1 Z = 1 Ans = 1

8 - CPRE 583 (Reconfigurable Computing): VHDL overview 1 Iowa State University (Ames) Some Key Differences from C C example VHDL example A = B + C X = Y + Z Ans = A + X Initially: A,B,C,X,Y,Z,Ans =1 A <= B + C X <= Y + Z Ans <= A + X Current Values: A = 2 B = 1 C = 1 X = 2 Y = 1 Z = 1 Ans = 4 Current Values: A = 1 B = 1 C = 1 X = 1 Y = 1 Z = 1 Ans = 1

9 - CPRE 583 (Reconfigurable Computing): VHDL overview 1 Iowa State University (Ames) Some Key Differences from C C example VHDL example A = B + C X = Y + Z Ans = A + X Initially: A,B,C,X,Y,Z,Ans =1 A <= B + C X <= Y + Z Ans <= A + X Current Values: A = 2 B = 1 C = 1 X = 2 Y = 1 Z = 1 Ans = 4 Current Values: A = 1 B = 1 C = 1 X = 1 Y = 1 Z = 1 Ans = 1 “Simulates in parallel ever delta time step”

10 - CPRE 583 (Reconfigurable Computing): VHDL overview 1 Iowa State University (Ames) Some Key Differences from C C example VHDL example A = B + C X = Y + Z Ans = A + X Initially: A,B,C,X,Y,Z,Ans =1 A <= B + C X <= Y + Z Ans <= A + X Current Values: A = 2 B = 1 C = 1 X = 2 Y = 1 Z = 1 Ans = 4 Current Values: A = 1 B = 1 C = 1 X = 1 Y = 1 Z = 1 Ans = 1 “Simulates in parallel ever delta time step” Snap shot after input change

11 - CPRE 583 (Reconfigurable Computing): VHDL overview 1 Iowa State University (Ames) Some Key Differences from C C example VHDL example A = B + C X = Y + Z Ans = A + X Initially: A,B,C,X,Y,Z,Ans =1 A <= B + C X <= Y + Z Ans <= A + X Current Values: A = 2 B = 1 C = 1 X = 2 Y = 1 Z = 1 Ans = 4 Current Values: A = 2 B = 1 C = 1 X = 2 Y = 1 Z = 1 Ans = 2 “Simulates in parallel ever delta time step”

12 - CPRE 583 (Reconfigurable Computing): VHDL overview 1 Iowa State University (Ames) Some Key Differences from C C example VHDL example A = B + C X = Y + Z Ans = A + X Initially: A,B,C,X,Y,Z,Ans =1 A <= B + C X <= Y + Z Ans <= A + X Current Values: A = 2 B = 1 C = 1 X = 2 Y = 1 Z = 1 Ans = 4 Current Values: A = 2 B = 1 C = 1 X = 2 Y = 1 Z = 1 Ans = 2 “Simulates in parallel ever delta time step” Different

13 - CPRE 583 (Reconfigurable Computing): VHDL overview 1 Iowa State University (Ames) Some Key Differences from C C example VHDL example A = B + C X = Y + Z Ans = A + X Initially: A,B,C,X,Y,Z,Ans =1 A <= B + C X <= Y + Z Ans <= A + X Current Values: A = 2 B = 1 C = 1 X = 2 Y = 1 Z = 1 Ans = 4 Current Values: A = 2 B = 1 C = 1 X = 2 Y = 1 Z = 1 Ans = 2 “Simulates in parallel ever delta time step” Snap shot after input change

14 - CPRE 583 (Reconfigurable Computing): VHDL overview 1 Iowa State University (Ames) Some Key Differences from C C example VHDL example A = B + C X = Y + Z Ans = A + X Initially: A,B,C,X,Y,Z,Ans =1 A <= B + C X <= Y + Z Ans <= A + X Current Values: A = 2 B = 1 C = 1 X = 2 Y = 1 Z = 1 Ans = 4 Current Values: A = 2 B = 1 C = 1 X = 2 Y = 1 Z = 1 Ans = 2 “Simulates in parallel ever delta time step”

15 - CPRE 583 (Reconfigurable Computing): VHDL overview 1 Iowa State University (Ames) Some Key Differences from C C example VHDL example A = B + C X = Y + Z Ans = A + X Initially: A,B,C,X,Y,Z,Ans =1 A <= B + C X <= Y + Z Ans <= A + X Current Values: A = 2 B = 1 C = 1 X = 2 Y = 1 Z = 1 Ans = 4 Current Values: A = 2 B = 1 C = 1 X = 2 Y = 1 Z = 1 Ans = 4 “Simulates in parallel ever delta time step”

16 - CPRE 583 (Reconfigurable Computing): VHDL overview 1 Iowa State University (Ames) Some Key Differences from C C example VHDL example Ans = A + X A = B + C X = Y + Z Initially: A,B,C,X,Y,Z,Ans =1 Ans <= A + X A <= B + C X <= Y + Z Current Values: A = 1 B = 1 C = 1 X = 1 Y = 1 Z = 1 Ans = 1 Current Values: A = 1 B = 1 C = 1 X = 1 Y = 1 Z = 1 Ans = 1 Change order of statements

17 - CPRE 583 (Reconfigurable Computing): VHDL overview 1 Iowa State University (Ames) Corresponding circuit VHDL example Initially: A,B,C,X,Y,Z,Ans =1 A <= B + C X <= Y + Z Ans <= A + X “Simulates in parallel ever delta time step”

18 - CPRE 583 (Reconfigurable Computing): VHDL overview 1 Iowa State University (Ames) Corresponding circuit VHDL example Initially: A,B,C,X,Y,Z,Ans =1 A <= B + C X <= Y + Z Ans <= A + X “Simulates in parallel ever delta time step” + + B(1) C(1) Y(1) Z(1) + A(1) X(1) Ans(1)

19 - CPRE 583 (Reconfigurable Computing): VHDL overview 1 Iowa State University (Ames) Corresponding circuit VHDL example Initially: A,B,C,X,Y,Z,Ans =1 A <= B + C X <= Y + Z Ans <= A + X “Simulates in parallel ever delta time step” + + B(1) C(1) Y(1) Z(1) + A(2) X(2) Ans(2)

20 - CPRE 583 (Reconfigurable Computing): VHDL overview 1 Iowa State University (Ames) Corresponding circuit VHDL example Initially: A,B,C,X,Y,Z,Ans =1 A <= B + C X <= Y + Z Ans <= A + X “Simulates in parallel ever delta time step” + + B(1) C(1) Y(1) Z(1) + A(2) X(2) Ans(4)

21 - CPRE 583 (Reconfigurable Computing): VHDL overview 1 Iowa State University (Ames) Corresponding circuit (More realistic) VHDL example Initially: A,B,C,X,Y,Z,Ans =1 A <= B + C after 2ns X <= Y + Z after 2ns Ans <= A + X after 2ns “Simulates in parallel ever delta time step” + + B(1) C(1) Y(1) Z(1) + A(1) X(1) Ans(1) 2ns

22 - CPRE 583 (Reconfigurable Computing): VHDL overview 1 Iowa State University (Ames) VHDL example Initially: A,B,C,X,Y,Z,Ans =1 “Simulates in parallel ever delta time step” + + B(1) C(1) Y(1) Z(1) + A(2) X(2) Ans(2) Corresponding circuit (More realistic) 2ns A <= B + C after 2ns X <= Y + Z after 2ns Ans <= A + X after 2ns

23 - CPRE 583 (Reconfigurable Computing): VHDL overview 1 Iowa State University (Ames) VHDL example Initially: A,B,C,X,Y,Z,Ans =1 “Simulates in parallel ever delta time step” + + B(1) C(1) Y(1) Z(1) + A(2) X(2) Ans(4) Corresponding circuit (More realistic) 2ns A <= B + C after 2ns X <= Y + Z after 2ns Ans <= A + X after 2ns

24 - CPRE 583 (Reconfigurable Computing): VHDL overview 1 Iowa State University (Ames) Typical Structure of a VHDL File LIBRARY ieee; ENTITY test_circuit IS PORT(B,C,Y,Z,Ans); END test_circuit; ARCHITECTURE structure OF test_circuit IS signal A : std_logic_vector(7 downto 0); signal X : std_logic_vector(7 downto 0); BEGIN A <= B + C; X <= Y + Z; Ans <= A + X; END Include Libraries Define component name and Input/output ports Declare internal signals, components Implement components functionality

25 - CPRE 583 (Reconfigurable Computing): VHDL overview 1 Iowa State University (Ames) Process Process provide a level serialization in VHDL (e.g. variables, clocked processes) Help separate and add structure to VHDL design

26 - CPRE 583 (Reconfigurable Computing): VHDL overview 1 Iowa State University (Ames) Process Example BEGIN My_process_1 : process (A,B,C,X,Y,Z) Begin A <= B + C; X <= Y + Z; Ans <= A + X; End My_process_1; My_process_2 : process (B,X,Y,Ans1) Begin A <= B + 1; X <= B + Y; Ans2 <= Ans1 + X; End My_process_2; END; Sensitivity list: specify inputs to the process. Process is updated when a specified input changes

27 - CPRE 583 (Reconfigurable Computing): VHDL overview 1 Iowa State University (Ames) Process Example (Multiple Drivers) BEGIN My_process_1 : process (A,B,C,X,Y,Z) Begin A <= B + C; X <= Y + Z; Ans <= A + X; End My_process_1; My_process_2 : process (B,X,Y,Ans1) Begin A <= B + 1; X <= B + Y; Ans2 <= Ans1 + X; End My_process_2; END; A signal can only be Driven (written) by one process. But can be read by many Compile or simulator may give a “multiple driver” Error or Warning message

28 - CPRE 583 (Reconfigurable Computing): VHDL overview 1 Iowa State University (Ames) Process Example (Multiple Drivers) BEGIN My_process_1 : process (A,B,C,X,Y,Z) Begin A <= B + C; X <= Y + Z; Ans <= A + X; End My_process_1; My_process_2 : process (B,X,Y,Ans1) Begin A1 <= B + 1; X1 <= B + Y; Ans2 <= Ans1 + X; End My_process_2; END; Maybe A,X were suppose to be A1,X1. Cut and paste error. Or may need to rethink Hardware structure to remove multiple driver issue.

29 - CPRE 583 (Reconfigurable Computing): VHDL overview 1 Iowa State University (Ames) Process Example (if-statement) BEGIN My_process_1 : process (A,B,C,X,Y,Z) Begin if (B = 0) then C <= A + B; Z <= X + Y; Ans1 <= A + X; else C <= 1; Z <= 0; Ans1 <= 1; end if; End My_process_1; END;

30 - CPRE 583 (Reconfigurable Computing): VHDL overview 1 Iowa State University (Ames) Clock Process Example BEGIN My_process_1 : process (clk) Begin IF (clk’event and clk = ‘1’) THEN C <= A or B; Z <= X or Y; Ans <= C and Z; END IF; End My_process_1; END; or A() B() X() Y() and C() Z() Ans() circuit not clocked

31 - CPRE 583 (Reconfigurable Computing): VHDL overview 1 Iowa State University (Ames) Clock Process Example BEGIN My_process_1 : process (clk) Begin IF (clk’event and clk = ‘1’) THEN C <= A or B; Z <= X or Y; Ans <= C and Z; END IF; End My_process_1; END; or A() B() X() Y() and C() Z() Ans() circuit with clock clk D Flip-Flop DFF Register

32 - CPRE 583 (Reconfigurable Computing): VHDL overview 1 Iowa State University (Ames) Clock Process Example BEGIN My_process_1 : process (clk) Begin IF (clk’event and clk = ‘1’) THEN C <= A or B; Z <= X or Y; Ans <= C and Z; END IF; End My_process_1; END; or A() B() X() Y() and C() Z() Ans() circuit with clock clk

33 - CPRE 583 (Reconfigurable Computing): VHDL overview 1 Iowa State University (Ames) Clock Process Example 2 BEGIN My_process_1 : process (clk) Begin IF (clk’event and clk = ‘1’) THEN C <= A xor B; Z <= X or Y; Ans <= C xor Z; END IF; End My_process_1; END; xor or A() B() X() Y() xor C() Z() Ans() circuit with clock clk

34 - CPRE 583 (Reconfigurable Computing): VHDL overview 1 Iowa State University (Ames) Clock Process Example 2 (Answer) BEGIN My_process_1 : process (clk) Begin IF (clk’event and clk = ‘1’) THEN C <= A xor B; Z <= X or Y; Ans <= C xor Z; END IF; End My_process_1; END; xor or A() B() X() Y() xor C() Z() Ans() circuit with clock clk

35 - CPRE 583 (Reconfigurable Computing): VHDL overview 1 Iowa State University (Ames) VHDL Constructs Entity Process Signal, Variable, Constants, Integers Array, Record VHDL on-line tutorials:

36 - CPRE 583 (Reconfigurable Computing): VHDL overview 1 Iowa State University (Ames) Signals and Variables Signals –Updated at the end of a process –Have file scope Variables –Updated instantaneously –Have process scope

37 - CPRE 583 (Reconfigurable Computing): VHDL overview 1 Iowa State University (Ames) std_logic, std_logic_vector Very common data types std_logic –Single bit value –Values: U, X, 0, 1, Z, W, H, L, - –Example: signal A : std_logic; A <= ‘1’; Std_logic_vector: is an array of std_logic –Example: signal A : std_logic_vector (4 downto 0); A <= x“00Z001”

38 - CPRE 583 (Reconfigurable Computing): VHDL overview 1 Iowa State University (Ames) Std_logic values –U : Uninitialized (signal has not been assigned a value yet) –X : Unknow (2 drivers one ‘0’ one ‘1’) –H : weak ‘1’ (example: model pull-up resister) I have never used this value –L : weak ‘0’ Time step 0

39 - CPRE 583 (Reconfigurable Computing): VHDL overview 1 Iowa State University (Ames) Std_logic values –U : Uninitialized (signal has not been assigned a value yet) –X : Unknow (2 drivers one ‘0’ one ‘1’) –H : weak ‘1’ (example: model pull-up resister) I have never used this value –L : weak ‘0’ Time step 0 1 UUU Std_logic values

40 - CPRE 583 (Reconfigurable Computing): VHDL overview 1 Iowa State University (Ames) Std_logic values –U : Uninitialized (signal has not been assigned a value yet) –X : Unknow (2 drivers one ‘0’ one ‘1’) –H : weak ‘1’ (example: model pull-up resister) I have never used this value –L : weak ‘0’ Time step 1 0 1UU Std_logic values

41 - CPRE 583 (Reconfigurable Computing): VHDL overview 1 Iowa State University (Ames) Std_logic values –U : Uninitialized (signal has not been assigned a value yet) –X : Unknow (2 drivers one ‘0’ one ‘1’) –H : weak ‘1’ (example: model pull-up resister) I have never used this value –L : weak ‘0’ Time step U Std_logic values

42 - CPRE 583 (Reconfigurable Computing): VHDL overview 1 Iowa State University (Ames) Std_logic values –U : Uninitialized (signal has not been assigned a value yet) –X : Unknow (2 drivers one ‘0’ one ‘1’) –H : weak ‘1’ (example: model pull-up resister) I have never used this value –L : weak ‘0’ Time step Std_logic values

43 - CPRE 583 (Reconfigurable Computing): VHDL overview 1 Iowa State University (Ames) Std_logic values –U : Uninitialized (signal has not been assigned a value yet) –X : Unknow (2 drivers one ‘0’ one ‘1’) –H : weak ‘1’ (example: model pull-up resister) I have never used this value –L : weak ‘0’ Time step X Std_logic values

44 - CPRE 583 (Reconfigurable Computing): VHDL overview 1 Iowa State University (Ames) Std_logic values –U : Uninitialized (signal has not been assigned a value yet) –X : Unknow (2 drivers one ‘0’ one ‘1’) –H : weak ‘1’ (example: model pull-up resister) I have never used this value –L : weak ‘0’ Time step X 1 0 Std_logic values

45 - CPRE 583 (Reconfigurable Computing): VHDL overview 1 Iowa State University (Ames) Std_logic values –U : Uninitialized (signal has not been assigned a value yet) –X : Unknow (2 drivers one ‘0’ one ‘1’) –H : weak ‘1’ (example: model pull-up resister) I have never used this value –L : weak ‘0’ Time step X 0 0 X 1 X Std_logic values

46 - CPRE 583 (Reconfigurable Computing): VHDL overview 1 Iowa State University (Ames) Std_logic values –U : Uninitialized (signal has not been assigned a value yet) –X : Unknow (2 drivers one ‘0’ one ‘1’) –H : weak ‘1’ (example: model pull-up resister) I have never used this value –L : weak ‘0’ Time step 0 ‘1’ Pull-up resistor Std_logic values

47 - CPRE 583 (Reconfigurable Computing): VHDL overview 1 Iowa State University (Ames) Std_logic values –U : Uninitialized (signal has not been assigned a value yet) –X : Unknow (2 drivers one ‘0’ one ‘1’) –H : weak ‘1’ (example: model pull-up resister) I have never used this value –L : weak ‘0’ Time step 0 0 U HU ‘1’ Pull-up resistor Std_logic values

48 - CPRE 583 (Reconfigurable Computing): VHDL overview 1 Iowa State University (Ames) Std_logic values –U : Uninitialized (signal has not been assigned a value yet) –X : Unknow (2 drivers one ‘0’ one ‘1’) –H : weak ‘1’ (example: model pull-up resister) I have never used this value –L : weak ‘0’ Time step H1 ‘1’ Pull-up resistor Std_logic values

49 - CPRE 583 (Reconfigurable Computing): VHDL overview 1 Iowa State University (Ames) Std_logic values –U : Uninitialized (signal has not been assigned a value yet) –X : Unknow (2 drivers one ‘0’ one ‘1’) –H : weak ‘1’ (example: model pull-up resister) I have never used this value –L : weak ‘0’ Time step ‘1’ Pull-up resistor Resolution(H,0) = 0 Std_logic values

50 - CPRE 583 (Reconfigurable Computing): VHDL overview 1 Iowa State University (Ames) mysignal’event (mysignal changed value) mysignal’high (highest value of mysignal’s type) mysignal’low Many other attributes – Pre-defined VHDL attributes

51 - CPRE 583 (Reconfigurable Computing): VHDL overview 1 Iowa State University (Ames) Signal: global to file Variable: local to process Singal vs Varible scope My_process_1 : process (B,C,Y) Begin A <= B + C; Z <= Y + C; End My_process_1; My_process_2 : process (B,X,Y,Ans1) Begin X <= Z + 1; Ans <= B + Y; End My_process_2;

52 - CPRE 583 (Reconfigurable Computing): VHDL overview 1 Iowa State University (Ames) Signal: global to file Variable: local to process Singal vs Varible scope My_process_1 : process (B,C,Y) Begin A <= B + C; varZ <= Y + C; End My_process_1; My_process_2 : process (B,X,Y,Ans1) Begin X <= varZ + 1; Ans <= B + Y; End My_process_2; Each varZ are local to their process. Completely independent

53 - CPRE 583 (Reconfigurable Computing): VHDL overview 1 Iowa State University (Ames) Arrays and Records Arrays: Group signals of the same type together Records: Group signal of different types together VHDL on-line tutorials:

54 - CPRE 583 (Reconfigurable Computing): VHDL overview 1 Iowa State University (Ames) Array Example (Delay Shift Register) flag_inflag_1flag_2flag_3 flag_out BEGIN My_process_1 : process (clk) Begin IF (clk’event and clk = ‘1’) THEN flag_1 <= flag_in; flag_2 <= flag_1; flag_3 <= flag_2; END IF; End My_process_1; flag_out <= flag_3 END;

55 - CPRE 583 (Reconfigurable Computing): VHDL overview 1 Iowa State University (Ames) Array Example (Delay Shift Register) flag_inflag_1flag_20 flag_out BEGIN My_process_1 : process (clk) Begin IF (clk’event and clk = ‘1’) THEN flag_1 <= flag_in; flag_2 <= flag_1; flag_20 <= flag_19; END IF; End My_process_1; flag_out <= flag_20 END;

56 - CPRE 583 (Reconfigurable Computing): VHDL overview 1 Iowa State University (Ames) Array Example (Delay Shift Register) flag_inflag_1flag_20 flag_out BEGIN My_process_1 : process (clk) Begin IF (clk’event and clk = ‘1’) THEN flag_reg(flag_reg'high downto 0) <= flag_reg(flag_reg'high-1 downto 0) & flag_in; END IF; End My_process_1; flag_out <= flag_reg(flag_reg'high); END; type flag_reg_array is array (DELAY-1 downto 0) of std_logic; signal flag_reg : flag_reg_array;

57 - CPRE 583 (Reconfigurable Computing): VHDL overview 1 Iowa State University (Ames) Array Example (Delay Shift Register) flag_reg(flag_reg'high downto 0)<= flag_reg(flag_reg'high-1 downto 0) & flag_in; flag_inflag(0)flag(1)flag(2) flag_out flag_inflag(0)flag(1)flag(2) flag_out 100 flag_inflag(0)flag(1)flag(2) flag_out 001 1

58 - CPRE 583 (Reconfigurable Computing): VHDL overview 1 Iowa State University (Ames) Detailed in class design next Friday

59 - CPRE 583 (Reconfigurable Computing): VHDL overview 1 Iowa State University (Ames) HW1

60 - CPRE 583 (Reconfigurable Computing): VHDL overview 1 Iowa State University (Ames) Questions/Comments/Concerns