Construction of Latency-Bounded Clock Trees Rickard Ewetz, Chuan Yean Tan, Cheng-Kok Koh Purdue University

On-Chip Variations 175 ps225 ps i j 75 ps125 ps Process variations Voltage variations Temperature variations

Outline Motivation Problem Formulation Proposed Latency Constraint Graph (LCG) Proposed Tree Construction Framework Experimental Results and Future Work

Skew Constraints Combinational Logic FF i FF j Setup time: Hold time: DDD

Clock Tree Synthesis Objective: Connect source to sinks – Buffers – Wires Constraints: – Transition time – Skew D Q Clock Source Clock Sinks a b c d wire buffer

Clock Tree Synthesis

On-Chip Variations D Q Clock Sinks a b c d CCA(a,b) CCA(b,c) Estimate OCV Delay variations by OCV and Safety margin

Problem Formulation (1) Estimate and. (2) Construct clock trees with and. Construct a clock tree with and !

-30 = = = = 10 SCG and Safety Margins D Q a b c d Find: a b c d With Safety Margin to OCV

20 30 Greedy-UST/DME D Q a b c d Source FSR ab = [-d ab, d ba ] [17] C.-W. A. Tsao and C.-K. Koh. UST/DME: a clock tree router for general skew constraints. ACM TODAES, pages 359–379, a b d c

Construction of Latency-Bounded Clock Trees 175 ps225 ps D Q i j 75 ps125 ps

Latency a b c a b c The latency is dependent on the subtree latencies and the skew constraints

Proposed Latency Constraint Graph (LCG) abc Latency Path SCG Virtual sink Virtual source LCG (negative) Bottom-up shortest path to vertex i: =[65, 55, 40] - (0 +(-10) +(-15)+(-40) = [65, 55, 40]

Root Construction a b c c a b LCG Compute delay insertions Minimum latency and maximal sharing of delay insertions

Root Construction Sort based on Topology selection Inexact Delay Realization a b c Maximal sharing of delay insertions 25 c a b

Tree Construction Delay insertions Skew commitments abc Virtual source Delay insertion Skew commitment -(40 +X ) a a -15 Delay insertion

Latency-Bounded Tree Construction abc Virtual source Virtual sink Feasible latency range -5 FLSR FSR FLR a b c

Virtual latency Root location abc Virtual source Virtual sink Virtual latency = d root * c delay ( )

Flow CTS CTO Input Output Merging Buffer insertion Input to CTS Output from CTS Subtree dragging Latency Aware Merging Latency locking Update of virtual latency Root construction

Experimental Setup Arbitrary skew constraints Monte Carlo Framework with on-chip variations – Process variations – Voltage variations – Temperature variations NameSinksSkew constraints scaled_s ecg aes [14] C. N. Sze ISPD 2010 high performance clock network synthesis contest: benchmark suite and results. ISPD’10.

Various Safety Margins on ecg Before CTOAfter CTO Circu it Struc- ture M user Lat- ency (ps) Cap (pF) TNS (ps) WNS (ps) Yield (%) TNS (ps) WNS (ps) Yield (%) ecgTree in [8] Tree R-Tree ecgTree in [8] Tree R-Tree ecgTree in [8] Tree R-Tree [8] R. Ewetz and C-K. Koh A Useful Skew Tree Framework for Inserting Large Safety Margins. ISPD’15

Latency-Bounded Clock Trees Before CTOAfter CTO Circ uit Struc- ture M user (ps) L user (ps) Lat- ency (ps) Cap (pF) TNS (ps) WNS (ps) Yield (%) TNS (ps) WNS (ps) Yield (%) s15R-Tree25∞ L-R-Tree L-R-Tree ecgR-Tree30∞ L-R-Tree L-R-Tree aesR-Tree50∞ L-R-Tree L-R-Tree

Summary and Future Work Proposed a latency constraint graph Tree construction based on the LCG Estimate and. Questions?