EE141 © Digital Integrated Circuits 2nd Introduction 1 EE4271 VLSI Design Dr. Shiyan Hu Office: EERC 731 Adapted and modified from Digital Integrated Circuits: A Design Perspective by Jan M. Rabaey, Anantha Chandrakasan, and Borivoje Nikolic. Introduction

EE141 © Digital Integrated Circuits 2nd Introduction Class Time and Office Hour  Class Time: MWF 16:05-16:55 (EERC 218)  Office Hours: MWF 14:30-15:30 or by appointment, office: EERC 731  Textbook (required): Digital Integrated Circuits: A Design Perspective, second edition, by Jan M. Rabaey, Anantha Chandrakasan and Borivoje Nikolic, Prentice Hall,  Grading:  Homework 20%  Midterm 25%  Final 25%  Lab 30% 2

EE141 © Digital Integrated Circuits 2nd Introduction Course Website   Contact information of instructor   EERC 731  Instructor’s webpage: 3

EE141 © Digital Integrated Circuits 2nd Introduction 4 What is this course all about?  Introduction to digital integrated circuits.  CMOS devices and manufacturing technology. CMOS inverters and gates. Propagation delay, noise margins, and power dissipation. Combinatorial Circuits and Sequential circuits.  What will you learn?  Understanding, designing, and optimizing digital circuits with respect to different quality metrics: speed, power dissipation, cost, and reliability

EE141 © Digital Integrated Circuits 2nd Introduction 5 Agenda  Introduction: Issues in digital integrated circuit (IC) design  Device: MOS Transistors  Wire: R, L and C  Fabrication process  CMOS inverter  Combinational logic structures  Sequential logic gates  Timing/power optimizations on gate and interconnect  Design methodologies

EE141 © Digital Integrated Circuits 2nd Introduction 6 Introduction  Why is designing digital ICs different today than it was before?  What is the challenge?

EE141 © Digital Integrated Circuits 2nd Introduction The Transistor Revolution First transistor Bell Labs, 1948

EE141 © Digital Integrated Circuits 2nd Introduction The First Integrated Circuit First IC Jack Kilby Texas Instruments 1958

EE141 © Digital Integrated Circuits 2nd Introduction 9 Intel 4004 Micro-Processor Intel 4004 Micro-Processor transistors 1 MHz operation

EE141 © Digital Integrated Circuits 2nd Introduction Intel 8080 Micro-Processor transistors

EE141 © Digital Integrated Circuits 2nd Introduction 11 Intel Pentium (IV) microprocessor million transistors 1.5 GHz

EE141 © Digital Integrated Circuits 2nd Introduction 12 Moore’s Law lIn 1965, Gordon Moore noted that the number of transistors on a chip doubled every 18 to 24 months. lHe made a prediction that semiconductor technology will double its effectiveness every 18 months

EE141 © Digital Integrated Circuits 2nd Introduction 13 Moore’s Law Electronics, April 19, 1965.

EE141 © Digital Integrated Circuits 2nd Introduction 14 Evolution in Memory Complexity

EE141 © Digital Integrated Circuits 2nd Introduction 15 Transistor Counts 1,000, ,000 10,000 1, i386 i486 Pentium ® Pentium ® Pro K 1 Billion Transistors Source: Intel Projected Pentium ® II Pentium ® III Courtesy, Intel

EE141 © Digital Integrated Circuits 2nd Introduction 16 ITRS Prediction

EE141 © Digital Integrated Circuits 2nd Introduction 17 Moore’s law in Microprocessors Pentium® proc P Year Transistors (MT) 2X growth in 1.96 years! Transistors on Lead Microprocessors double every 2 years Courtesy, Intel

EE141 © Digital Integrated Circuits 2nd Introduction 18 Frequency P6 Pentium ® proc Year Frequency (Mhz) Lead Microprocessors frequency doubles every 2 years Doubles every 2 years Courtesy, Intel

EE141 © Digital Integrated Circuits 2nd Introduction 19 Power Dissipation P6 Pentium ® proc Year Power (Watts) Lead Microprocessors power continues to increase Courtesy, Intel

EE141 © Digital Integrated Circuits 2nd Introduction 20 Power is a major problem 5KW 18KW 1.5KW 500W Pentium® proc Year Power (Watts) Power delivery and dissipation will be prohibitive Courtesy, Intel

EE141 © Digital Integrated Circuits 2nd Introduction 21 Power density Pentium® proc P Year Power Density (W/cm2) Hot Plate Nuclear Reactor Rocket Nozzle Power density too high to keep junctions at low temp Courtesy, Intel

EE141 © Digital Integrated Circuits 2nd Introduction 22 Not Only Microprocessors Digital Cellular Market (Phones Shipped) Units 48M 86M 162M 260M 435M Analog Baseband Digital Baseband (DSP + MCU ) Power Management Small Signal RF Power RF (data from Texas Instruments) Cell Phone

EE141 © Digital Integrated Circuits 2nd Introduction 23 Many Chips

EE141 © Digital Integrated Circuits 2nd Introduction 24 Challenges in Digital Design Ultra-high speed design Interconnect delay and noise Reliability, Manufacturability Power Dissipation Time to market

EE141 © Digital Integrated Circuits 2nd Introduction 25 Productivity Trends ,000 10, ,000 1,000,000 10,000, ,000 10, ,000 1,000,000 10,000, ,000,000 Logic Tr./Chip Tr./Staff Month. x x x x x x x 21%/Yr. compound Productivity growth rate x 58%/Yr. compounded Complexity growth rate 10,000 1, Logic Transistor per Chip (M) ,000 10, ,000 Productivity (K) Trans./Staff - Mo. Source: Sematech Complexity outpaces design productivity Complexity Courtesy, ITRS Roadmap

EE141 © Digital Integrated Circuits 2nd Introduction 26 Why Scaling?  Technology shrinks by 0.7 per generation  With every generation can integrate 2x more functions per chip  Chip price does not increase significantly  Cost of a function decreases by 2x  However,  Design engineering population does not double every two years.  How to design much more complex chips (with more and more functions)?  Great need for ultra-fast design methods  Design Automation (Computer-Aided Design)

EE141 © Digital Integrated Circuits 2nd Introduction 27 Design Abstraction Enables CAD n+ S G D + DEVICE CIRCUIT GATE MODULE SYSTEM

EE141 © Digital Integrated Circuits 2nd Introduction 28 Design Metrics  How to evaluate performance of a digital circuit (gate, block, …)?  Speed (delay, operating frequency)  Power dissipation  Cost –Design time –Design effort  Reliability –Process, voltage and temperature variations

EE141 © Digital Integrated Circuits 2nd Introduction 29 Cost of Integrated Circuits  NRE (non-recurrent engineering) costs  design time and effort to design layout and mask  one-time cost factor  Recurrent costs  silicon processing, packaging, test  proportional to volume  proportional to chip area

EE141 © Digital Integrated Circuits 2nd Introduction 30 NRE Cost is Increasing

EE141 © Digital Integrated Circuits 2nd Introduction 31 Die Cost Single die Wafer From Going up to 12” (30cm)

EE141 © Digital Integrated Circuits 2nd Introduction 32 Yield

EE141 © Digital Integrated Circuits 2nd Introduction 33 Defects  is approximately 3 in the current fabrication process About defect per cm 2.

EE141 © Digital Integrated Circuits 2nd Introduction 34 Some Examples (1994) ChipMetal layers Line width Wafer cost Def./ cm 2 Area mm 2 Dies/ wafer YieldDie cost 386DX 20.90$ %$4 486 DX $ %$12 Power PC $ %$53 HP PA $ %$73 DEC Alpha 30.70$ %$149 Super Sparc 30.70$ %$272 Pentium 30.80$ %$417

EE141 © Digital Integrated Circuits 2nd Introduction 35 Summary  Digital integrated circuit design faces huge challenges for the coming decades  High speed  Low power  Short design time for highly complex circuit having 1 billion transistors  Reliable under noise and variations  Purpose of the course  Understand the basics of VLSI design  Getting a clear perspective on the challenges and potential solutions