CMOS VLSI Design 4th Ed. EEL 6167: VLSI Design Wujie Wen, Assistant Professor Department of ECE Lecture 3A: CMOs Transistor Theory Slides adapted from Harris’ slides from Harvey Mudd. Copyright 2005 Addison-Wesley and Rabaey’s Digital Integrated Circuits, Copyright 2002, J. Rabaey et al.

CMOS VLSI Design 4th Ed. 3: CMOS Transistor Theory2 Outline  Introduction  MOS Capacitor  nMOS I-V Characteristics  pMOS I-V Characteristics  Gate and Diffusion Capacitance

CMOS VLSI Design 4th Ed. 3: CMOS Transistor Theory3 Introduction  So far, we have treated transistors as ideal switches  An ON transistor passes a finite amount of current –Depends on terminal voltages –Derive current-voltage (I-V) relationships  Transistor gate, source, drain all have capacitance –I = C (  V/  t) ->  t = (C/I)  V –Capacitance and current determine speed

CMOS VLSI Design 4th Ed. 3: CMOS Transistor Theory4 MOS Capacitor GGate and body form MOS capacitor OOperating modes –A–Accumulation –D–Depletion –I–Inversion

CMOS VLSI Design 4th Ed. 3: CMOS Transistor Theory5 Terminal Voltages  Mode of operation depends on V g, V d, V s –V gs = V g – V s –V gd = V g – V d –V ds = V d – V s = V gs - V gd  Source and drain are symmetric diffusion terminals –By convention, source is terminal at lower voltage –Hence V ds  0  nMOS body is grounded. First assume source is 0 too.  Three regions of operation –Cutoff –Linear –Saturation

CMOS VLSI Design 4th Ed. Threshold Voltage Concept 3: CMOS Transistor Theory6 The value of V GS where strong inversion occurs is called the threshold voltage, V T S D p substrate B G V GS + - n+ depletion region n channel

CMOS VLSI Design 4th Ed. Transistor in Cutoff Mode  V GS < V T  No channel  I DS = 0. 3: CMOS Transistor Theory7 S D B G n+ V GS V DS V GS < V T Assuming V GS < V T

CMOS VLSI Design 4th Ed. 3: CMOS Transistor Theory8 nMOS Cutoff  No channel  I ds ≈ 0

CMOS VLSI Design 4th Ed. Transistor in Linear Mode  Channel forms  Current flows from D to S –e - from S to D  Similar to linear R 3: CMOS Transistor Theory9 S D B G n+ V GS V DS IDID x V(x) -+ The current is a linear function of both V GS and V DS V GS > V T Assuming V GS > V T

CMOS VLSI Design 4th Ed. 3: CMOS Transistor Theory10 nMOS Linear  Channel forms  Current flows from d to s –e - from s to d  I ds increases with V ds  Similar to linear resistor

CMOS VLSI Design 4th Ed. Transistor in Saturation Mode  Channel pinch-off  I DS is independent of V DS. 3: CMOS Transistor Theory11 The current remains constant (saturates). V GS > V T, V DS > V GS - V T Assuming V GS > V T, V DS > V GS - V T S D B G V GS IDID V GS - V T -+ n+ Pinch-off V DS

CMOS VLSI Design 4th Ed. 3: CMOS Transistor Theory12 nMOS Saturation  Channel pinches off  I ds independent of V ds  We say current saturates  Similar to current source

CMOS VLSI Design 4th Ed. 3: CMOS Transistor Theory13 I-V Characteristics  In Linear region, I ds depends on –How much charge is in the channel? –How fast is the charge moving?

CMOS VLSI Design 4th Ed. 3: CMOS Transistor Theory14 Channel Charge  MOS structure looks like parallel plate capacitor while operating in inversions –Gate – oxide – channel  Q channel = CV  C = C g =  ox WL/t ox = C ox WL  V = V gc – V t = (V gs – V ds /2) – V t C ox =  ox / t ox

CMOS VLSI Design 4th Ed. 3: CMOS Transistor Theory15 Carrier velocity  Charge is carried by e-  Electrons are propelled by the lateral electric field between source and drain –E = V ds /L  Carrier velocity v proportional to lateral E-field –v =  E  called mobility  Time for carrier to cross channel: –t = L / v

CMOS VLSI Design 4th Ed. 3: CMOS Transistor Theory16 nMOS Linear I-V  Now we know –How much charge Q channel is in the channel –How much time t each carrier takes to cross

CMOS VLSI Design 4th Ed. 3: CMOS Transistor Theory17 nMOS Saturation I-V  If V gd < V t, channel pinches off near drain –When V ds > V dsat = V gs – V t  Now drain voltage no longer increases current

CMOS VLSI Design 4th Ed. 3: CMOS Transistor Theory18 nMOS I-V Summary  Shockley 1 st order transistor models

CMOS VLSI Design 4th Ed. I-V Relation: Saturation Mode  For long-channel devices (L>0.25μm)  When V DS ≥ V DSAT = V GS – V T since the voltage difference over the induced channel (from the pinch-off point to the source) remains fixed at V GS – V T.  However, the effective length of the conductive channel is modulated by the applied V DS, so where is the channel-length modulation (varies with the inverse of the channel length) 3: CMOS Transistor Theory19

CMOS VLSI Design 4th Ed. I ds Determinates  For a fixed V DS and V GS (> V T ), I DS is a function of L –the distance between the source and drain – L W –the channel width – W V T –the threshold voltage – V T t ox –the thickness of the SiO 2 – t ox  ox –the dielectric of the gate insulator (SiO 2 ) –  ox –the carrier mobility  nfor NMOS:  n = 500 cm 2 /V-sec  pfor PMOS:  p = 180 cm 2 /V-sec 3: CMOS Transistor Theory20

CMOS VLSI Design 4th Ed. I-V Plot (NMOS) 3: CMOS Transistor Theory21 I D (A) V DS (V) X V GS = 1.0V V GS = 1.5V V GS = 2.0V V GS = 2.5V LinearSaturation V DS = V GS - V T Quadratic dependence NMOS transistor, 0.25um, L d = 10um, W/L = 1.5, V DD = 2.5V, V T = 0.4V cut-off

CMOS VLSI Design 4th Ed. PMOS I-V Characteristics  All dopings and voltages are inverted for PMOS  Mobility  p is determined by holes –Typically 2-3x lower than that of electrons  n –120 cm 2 /V*s in AMI 0.6  m process  Thus PMOS must be wider to provide same current –In this class, assume  n /  p = 2 3: CMOS Transistor Theory22

CMOS VLSI Design 4th Ed. Short-Channel I-V Plot (PMOS) 3: CMOS Transistor Theory23 I D (A) V DS (V) X V GS = -1.0V V GS = -1.5V V GS = -2.0V V GS = -2.5V PMOS transistor, 0.25um, L d = 0.25um, W/L = 1.5, V DD = 2.5V, V T = -0.4V

CMOS VLSI Design 4th Ed. 3: CMOS Transistor Theory24 Capacitance  Any two conductors separated by an insulator have capacitance  Gate to channel capacitor is very important –Creates channel charge necessary for operation  Source and drain have capacitance to body –Across reverse-biased diodes –Called diffusion capacitance because it is associated with source/drain diffusion

CMOS VLSI Design 4th Ed. 3: CMOS Transistor Theory25 Gate Capacitance  Approximate channel as connected to source  C gs =  ox WL/t ox = C ox WL = C permicron W  C permicron is typically about 2 fF/  m

CMOS VLSI Design 4th Ed. 3: CMOS Transistor Theory26 Diffusion Capacitance  C sb, C db  Undesirable, called parasitic capacitance  Capacitance depends on area and perimeter –Use small diffusion nodes –Comparable to C g for contacted diff –½ C g for uncontacted –Varies with process

CMOS VLSI Design 4th Ed. Reading  Chapter 2 ( ) 0: Introduction27