Modern VLSI Design 3e: Chapter 8 Copyright  1998, 2002 Prentice Hall PTR Topics n Verilog register-transfer modeling: –basics using traffic light controller; –synthesis.

Modern VLSI Design 3e: Chapter 8 Copyright  1998, 2002 Prentice Hall PTR Verilog n Verilog was designed as an efficient simulation language. n Relatively simple, terse syntax. n Most popular HDL in use today.

Modern VLSI Design 3e: Chapter 8 Copyright  1998, 2002 Prentice Hall PTR Verilog formulas

Modern VLSI Design 3e: Chapter 8 Copyright  1998, 2002 Prentice Hall PTR Verilog constants n Bit constant: –0, 1 n Bit vector constant: –4’b1010

Modern VLSI Design 3e: Chapter 8 Copyright  1998, 2002 Prentice Hall PTR Some useful constructs ‘define aconst 2’b00 constant vector $monitor($time,,”a=%b, b=%b”,a,b); value monitor output #1 a=0; b=0 #2 a=1; b=0 sequence of waveforms

Modern VLSI Design 3e: Chapter 8 Copyright  1998, 2002 Prentice Hall PTR Four-valued OR function

Modern VLSI Design 3e: Chapter 8 Copyright  1998, 2002 Prentice Hall PTR Four-valued AND function

Modern VLSI Design 3e: Chapter 8 Copyright  1998, 2002 Prentice Hall PTR Verilog structural model Module adder(a,b,cin,sum,cout); input a, b, cin; output sum, cout; xor #2 s(sum,a,b,cin); // sum and #1 // carry out c1(x1,a,b); c2(x2,a,cin); c3(x3,b,cin); or #1 c4(cout,x1,x2,x3); endmodule Time delay for output Output wire Input wires

Modern VLSI Design 3e: Chapter 8 Copyright  1998, 2002 Prentice Hall PTR If statements if (b | c) then y = 1; else y <= 0; if (b | c) then y = 1; else z = a | b; y assigned value in both cases different net assigned in true, false cases

Modern VLSI Design 3e: Chapter 8 Copyright  1998, 2002 Prentice Hall PTR Conditional assignments if (b | c) then y = ‘1’; else z = a | b; n Simulation: –Condition is tested based on current signal states. –Only one net gets an event. n Synthesis: –Creates don’t-cares for y and z.

Modern VLSI Design 3e: Chapter 8 Copyright  1998, 2002 Prentice Hall PTR Loop statement n A loop performs an operation over an array of signals: for (i=0; i<N; i=i+1) x[i] = a[i] & b[i];

Modern VLSI Design 3e: Chapter 8 Copyright  1998, 2002 Prentice Hall PTR always statement always guards execution of a block of statements. –Block is always executed on the logical condition. n begin.. end

Modern VLSI Design 3e: Chapter 8 Copyright  1998, 2002 Prentice Hall PTR Structure of a Verilog model n Module statement. –Declares I/O pin names. n Declarations: –inputs and outputs; –registers. n Body.

Modern VLSI Design 3e: Chapter 8 Copyright  1998, 2002 Prentice Hall PTR A synthesizable Verilog archtiecture n Declarations of pins and registers. n Definitions of constants (similar to C #define statement). –‘define GREEN ‘2b11 n Combinational and sequential portions. statements.

Modern VLSI Design 3e: Chapter 8 Copyright  1998, 2002 Prentice Hall PTR Verilog combinational portion or short or long or cars) begin when HG: begin // state hwy-green highway_light = GREEN; farm_light = RED; if (cars & long) then begin ctrl_next = HY; start_timer = 1; end else begin ctrl_next - HG; start_timer = 0; end end

Modern VLSI Design 3e: Chapter 8 Copyright  1998, 2002 Prentice Hall PTR Verilog sequential portion clock or negedge reset) if (~reset) ctrl_state <= 0; else ctrl_state <= ctrl_next; end Condition on clock/reset Transfer of next state to current state

Modern VLSI Design 3e: Chapter 8 Copyright  1998, 2002 Prentice Hall PTR Testbench structure Unit under test (UUT) testbench tester

Modern VLSI Design 3e: Chapter 8 Copyright  1998, 2002 Prentice Hall PTR Verilog testbed organization n Module declaration. –Two components: UUT and tester. n Definition of UUT. n Definition of tester.

Modern VLSI Design 3e: Chapter 8 Copyright  1998, 2002 Prentice Hall PTR Testbench tester process initial begin $monitor($time,,”a=%b”,a); #1a=0; b=0; cin=0; #1 a=1; b=0; cin=0; #2 a=1; b=1; cin=1; end endmodule Test inputs Prints signal values