1 VLSI Algorithm & Computing Structures Chapter 1. Introduction to DSP Systems Younglok Kim Dept. of Electrical Engineering Sogang University Spring 2007

Dept. of Electrical Engineering, Sogang University 2 What will be covered in this course? DSP architectures & structures for high performance VLSI design Methodologies needed to design custom or semi- custom VLSI circuits NOT actual VLSI circuit or layout design Focus on design of efficient architectures for Less area for smaller chip size Less power consumption for longer battery lifetime Higher speed for real time processing Lower round-off noise

Dept. of Electrical Engineering, Sogang University 3 DSP Applications Video compression Digital set-top box Cable modems Portable video systems/computers Digital audio/radio Wireless communication Digital still camera Speech processing GPS (global positioning systems) Radar imaging Acoustic beamformer Biomedical signal processing Etc

Dept. of Electrical Engineering, Sogang University 4 DSP Architecture Examples For a speech applications, Low sampling rate Low speed requirement Prefer time-multiplexed architecture For a video applications, 10~100 giga operations per second One-to-one mapping of algorithm operations and processors

Dept. of Electrical Engineering, Sogang University 5 What to do for this class? Understanding the topics covered in the classroom Read book, papers or other material if needed. Solve the problems at the end of each chapter. Verify the DSP algorithm MatLab/C simulations DSP HDL etc

Dept. of Electrical Engineering, Sogang University 6 Class Materials Main Textbook VLSI Digital Signal Processing Systems, Keshab K. Parhi, John Wiley & Sons, Inc Lecture notes Papers and Materials will be recommended in the class

Dept. of Electrical Engineering, Sogang University 7 Organization of Textbook Part I: High-level architectural transformations Part II: High-level algorithm transformations Part III: VLSI architecture of arithmetic operations

Dept. of Electrical Engineering, Sogang University 8 High-level architectural transformations Iteration bound (ch.2) Pipelining and Parallel Processing (ch.3) Retiming techniques (ch4) Unfolding (ch.5) Folding (ch.6) Systolic array design methodology (ch.7)

Dept. of Electrical Engineering, Sogang University 9 High-level algorithm transformations Fast Convolution (ch.8) Strength reduction (ch.9) Look ahead and Relaxed look ahead (ch.10) Scaling and round-off noise (ch.11) Digital Lattice filter structures (ch.12)

Dept. of Electrical Engineering, Sogang University 10 VLSI architecture of arithmetic operations Addition, multiplication and digital filters (ch.13) Redundant arithmetic (ch.14) Numerical strength reduction (ch.15) Synchronous and Asynchronous pipelines (ch.16) Low-power design (ch.17) Architectures for programmable digital signal processors (ch.18)

11 Chapter 1 Introduction to DSP Systems

Dept. of Electrical Engineering, Sogang University 12 What is Digital Signal? A sequence of numbers having finite precision SamplerQuantizer Analog signal Discrete-Time signal Quantized signal Discrete-time Discrete-valued signal Coder Binary digital signal

Dept. of Electrical Engineering, Sogang University 13 Performance Measurements of Digital Design Amount of hardware circuitry and resources Space or area Execution speed Depends on both throughput and clock rate Amount of power dissipation Finite word length performance for fixed-point DSP systems Quantization error or round-off noise

Dept. of Electrical Engineering, Sogang University 14 Features of Digital Signal Processing over General Computations Real time throughput requirement Throughput needs to meet sample rate requirement Data driven property Enable the use of asynchronous systems

Dept. of Electrical Engineering, Sogang University 15 Overview of Typical DSP algorithms Convolution Correlation Digital Filters Adaptive Filters LMS adaptive filters Stochastic-Gradient adaptive lattice filter Motion Estimation Discrete Cosine Transform (DCT) Vector Quantization Viterbi Algorithm and Dynamic Programming Decimator and Expander Wavelets and Filter Banks

Dept. of Electrical Engineering, Sogang University 16 Some Definitions For DSP Algorithms Non-terminating programs Execute repetitively Iteration Execution of all the computations in the algorithm once Iteration period Execution time of one iteration Iteration rate Reciprocal of the iteration period

Dept. of Electrical Engineering, Sogang University 17 Some Definitions For DSP Systems Sampling rate Number of samples processed per second Path Proportional to the computation time Critical path for combinational logic circuit Longest path between inputs and outputs Critical path for sequential circuits Longest path between any two storage (delay) elements

Dept. of Electrical Engineering, Sogang University 18 Some Definitions For DSP Systems … Critical path computation time determines Minimum feasible clock period of DSP systems Latency Difference between the time an output generated and the time at which its corresponding input was received by the system Latency representations Absolute time units, or the number of gate delays, for combinational logic circuit systems. Number of clock cycle for the sequential systems.

Dept. of Electrical Engineering, Sogang University 19 3-Tap FIR Filter Example Each iteration generates one output sample with One input signal 3 multiplication operations (in parallel or serial) 2 addition operations Latency dependent on the architectures

Dept. of Electrical Engineering, Sogang University 20 Various Representations of DSP Systems DSP Algorithm Descriptions Behavioral Descriptions Graphical Representations

Dept. of Electrical Engineering, Sogang University 21 DSP algorithm descriptions Mathematical formulations Specify functionality of DSP algorithm Does not specify the order & structure of the internal operations Behavioral description languages or graphical representations for architectural design

Dept. of Electrical Engineering, Sogang University 22 Behavioral Descriptions Applicative languages A set of equations Silage language Prescriptive languages Specify the order of the assignment statements Pascal, C or Fortran Descriptive languages Represents the structure of DSP system Verilog HDL or VHDL

Dept. of Electrical Engineering, Sogang University 23 Graphical Representations Efficient for investigating and analyzing data flow properties Efficient for exploiting the inherent parallelism among different subtasks Easy mapping DSP algorithm descriptions to hardware structural implementations Provide technology-independent architecture

Dept. of Electrical Engineering, Sogang University 24 Various graphical representations Block Diagram Signal Flow Graph Data Flow Graph Dependence Graph

Dept. of Electrical Engineering, Sogang University 25 Block Diagram Captures the exact functionality of a system Consist of Functional block Directed edges Represents data flow from its input block to output block Contains non-negative delay element Various block diagrams can be derived for the same system with different realizations of the same functionality

Dept. of Electrical Engineering, Sogang University 26 Block Diagram of 3-Tap FIR Filter

Dept. of Electrical Engineering, Sogang University 27 Data-broadcast FIR filter

Dept. of Electrical Engineering, Sogang University 28 Signal Flow Graph Node Computations of tasks, ex: multipliers or adders Source node: node with no entering node Sink node: node with only entering node Directed edge Denotes the linear transformation from the signal at originating node to the signal at terminating node Cannot be used to describe multi-rate DSP systems

Dept. of Electrical Engineering, Sogang University 29 SFG of 3-Tap FIR Filter

Dept. of Electrical Engineering, Sogang University 30 Transposition of SFG SFG reversal (transposition) is only applicable to Linear networks Single input single output (SISO) systems Multi-input multi-output (MIMO) systems described by symmetric transformation matrices

Dept. of Electrical Engineering, Sogang University 31 Data-flow graphs (DFG) Generally used for high-level synthesis to derive concurrent implementations of DSP applications onto parallel hardware Node Computation or Function Directed edge Data path, communication between nodes Contains non-negative number of delays

Dept. of Electrical Engineering, Sogang University 32 BD & DFG Of Recursive Algorithm

Dept. of Electrical Engineering, Sogang University 33 Data-Driven Property of DFG Precedence constraint Node fires whenever all the input data are available A node with multiple input edges can only fire after all its precedent nodes have fired Intra-precedence constraint The edge has zero delay Inter-precedence constraint The edge has one or more delays Major concerns Subtask scheduling Resource allocation

Dept. of Electrical Engineering, Sogang University 34 Synchronous DFG (SDFG) The number of data samples produced or consumed by each node in each execution is specified a priori Single-rate SDFG example

Dept. of Electrical Engineering, Sogang University 35 SDFG of multi-rate DFGs Multi-rate Non-Synchronous DFG Multi-rate DFG

Dept. of Electrical Engineering, Sogang University 36 Processing Rate of Multi-Rate SDFG Frequency of each node = number of invocations of each node per iteration A, B, C are operated at different frequencies A processes f A input samples per time unit Produce 3f A output samples per time unit

Dept. of Electrical Engineering, Sogang University 37 Dependence Graph (DG) Shows the dependence of the computations Used for systolic array design Node Computation Edge Precedence constraint among nodes

Dept. of Electrical Engineering, Sogang University 38 2D DG OF FIR Filter Processing Element (PE)

Dept. of Electrical Engineering, Sogang University 39 Differences between DFG & DG DFG Shows only one iteration Contains delay elements Iterations are executed repetitively DG Shows all iterations No delay elements A node is NEVER reused