Upgrade Intro 10 Jan 2010 Norman Gee

N. Gee – Upgrade Introduction 2 LHC Peak Luminosity Lumi curve from F.Zimmermann : Nov Upgrade Week ? ?

N. Gee – Upgrade Introduction 3 LHC Plans LHC Machine used to plan two steps of luminosity increase –Now seems to be more of a continuous evolution –Exact dates very uncertain, tending to move later –But for ease of planning, ATLAS is still talking about two phases of upgrade “Phase I” : Ultimate luminosity ~3 x –Requires changes to collimators and new Linac (being built) –Main change in ATLAS is insertion of new inner detector b-layer (IBL) –Needs 6 month shutdown. ATLAS plans this for 2014, but must coincide with integration of new Linac into LHC “Phase 2” : Ultimate luminosity 5-10 x Beam in 2020? –10 35 very hard to handle; we prefer machine with “Luminosity Levelling”, detunes machine to reduce peak luminosity and retunes as beam current & quality decline – gives 5 x –ATLAS Major rework -18 month shutdown: new inner detector & forward calorimetry, digital calorimeter readout, muon chambers & electronics

N. Gee – Upgrade Introduction 4 TDAQ Upgrade Activities TDAQ R&D Proposal developed in 2009 –Agreed by TDAQ Institute Board, Signed by 90% of TDAQ institutes –Submitted to ATLAS Upgrade Steering Group, now under review When they agree, final step would be approval by ATLAS Exec Board –Defines 9 work package areas (One common, 5 Phase I, 3 Phase II) First All-of-Level-1 Meeting to start cross-Level-1 discussions (like RD27) –Identify missing details – e.g. what signals come from Muon into Topo Processor, what exactly is required from upgraded CTP –New TDAQ Upgrade Twiki area under development (T Perez) ATLAS Letter of Intent (to LHCC) describing ATLAS Phase-II plans TDAQ chapter in LoI partly written –Currently based on R&D proposal text; needs more definite strawman –To be included in TDAQ Open meeting 18 Jan –Second draft to be circulated mid-February

N. Gee – Upgrade Introduction 5 Phase I – Level-1 Issues Luminosity 3x. No change to most detector electronics (not enough time) –Keep within same maximum trigger rate – or less (readout limits) –Must stay in 2.5  s latency envelope (less is better for LAr) –Events per bunch crossing rises from 20 events at design luminosity to ~60. Isolation thresholds may have to be raised to control rates –But raising trigger thresholds kills physics signatures No change in analogue info from calorimeters –Possibility of improved pulse handling (MCM upgrade studies) Proposal to add topological processing (also involves L1Muon and AFP) L1Muon studying addition of Tilecal rear sampling to muon trigger CTP firmware upgrade to accept more input bits (faster input links) Hence current studies –Monte Carlo studies (what benefit do topological algorithms bring?) Monte Carlo has difficulties with pileup. Results essential for Ph I & II design –Architectural studies –Technology demonstrators

N. Gee – Upgrade Introduction 6 Phase II: Level-1 Muon Trigger Rate Kunihiro Nagano (Rome TDAQ week) CSC rates for b/c/W are well reproduced by this resolution convolution method The determining factor is resolution L2 muFast: better resolution than L1 by using MDT L2 muComb: better resolution than muFast by combining to ID track L1 rate is >100kHz with MU20, >50 kHz with MU40 How the rate improves with resolution improvement can be guessed from this plot

N. Gee – Upgrade Introduction 7 Phase II – Level-1 Triggers L1Muon proposals to add additional chambers to improve P T resolution –Use of MDTs needs more latency? L1Calo Upgrade plan is to use finer-grain calo signals –This will allow some selection algorithms like those used today in Level-2 (use shower profile) Need to produce isolation signals for L1Muon –Not obvious that jets are best for this Proposals to add a Level-1 Track Trigger –Primary aim to help with muon trigger rate –May also help with electron identification

N. Gee – Upgrade Introduction 8 L1Track – Two Options Track trigger needs (partial) tracker readout, but can’t read out selected layers at 40MHz Either : Standalone, using radially-adjacent silicon layers –Layers are electrically connected (radial chips) –Coincidence logic identifies high-PT tracks –Coincidence data are read out for every bunch crossing, & processed off detector Or (preferred): Regional tracker readout round RoIs from L1Calo/L1Muon –L1Calo/L1Muon reduce rate from 40MHz to ~400kHz “L0A” –A few (~4) Regions of Interest (RoIs) identified, readout requests sent to tracker modules within the RoIs –Only a few % of tracker is read out per L0A In both cases, readout is priority multiplexed into main silicon readout 8

N. Gee – Upgrade Introduction 9 Current Level-1 Hardware Trigger

N. Gee – Upgrade Introduction 10 Possible Phase I Level-1 Trigger

N. Gee – Upgrade Introduction 11 Possible Phase-II Hardware Trigger

N. Gee – Upgrade Introduction 12 Activities in L1Calo reporting today Monte Carlo Simulation Hardware R&D & Technology Demonstrators Architecture Studies This evening… Management discussion of institute responsibilities