SRC: instruction formats Op-coderarb rc c Type D Op-code Type Aunused Op-codera Type Bc1 21 Op-coderarb Type C c2

CS501 Advanced Computer Architecture Lecture04 Dr.Noor Muhammad Sheikh

Encoding for the GPRs to be used in place of ra, rb, or rc RegisterCodeRegisterCodeRegisterCodeRegisterCode R000000R801000R R R100001R901001R R R200010R R R R300011R R R R400100R R R R500101R R R R600110R R R R700111R R R Notes: simple 5-bit encoding as shown above; ra, rb, rc are names of fields, used as “place-holders”, and can represent any one of these 32 registers. Except: rb =0 does not mean R0; explained later

Type A Op-code unused  Only two instructions  nop (op-code = 0) useful in pipelining  stop (op-code = 31)  Both are 0-operand

 three instructions; all three use relative addressing mode  ldr (op-code = 2 ) load register from memory using relative address ldr R3, 56R[3] M[PC+56]  lar (op-code = 6 ) load register with relative address lar R3, 56R[3] PC+56  str (op-code = 4) store register to memory using relative address str R8, 34M[PC+34] R[8]  the effective address is computed at run-time by adding a constant to the PC  makes the instructions relocatable Type B Op-codera c1 21 Note: R8 is register name and R[8] means contents of register R8

Type C Op-coderarb c2  three load/store instructions, plus three ALU instructions  ld (op-code = 1 ) load register from memory ld R3, 56 R[3] M[56] (rb field = 0) ld R3, 56(R5)R[3] M[56+R[5]] (rb field ≠ 0)  la (op-code = 5 ) load register with displacement address la R3, 56R[3] 56 la R3, 56(R5)R[3] 56+R[5]  st (op-code = 3 ) store register to memory st R8, 34M[34]R[8] st R8, 34(R6)M[34+R[6]] R[8] direct addressing mode Indexed addressing mode Immediate addressing mode Indexed addressing mode direct addressing mode

Type C (continued…) Op-coderarb c2  ….and the three ALU instructions  addi (op-code = 13) immediate 2’s complement addition addi R3, R4, 56 R[3] R[4]+56 (rb field = R4)  andi (op-code = 21) immediate logical AND andi R3, R4, 56R[3] R[4]&56  ori (op-code = 23) immediate logical OR ori R3, R4, 56R[3] R[4]~56 Note special symbol used for AND If the constant is negative, this becomes a subtract instruction register addressing mode

Type C (modified form) Op-coderarb unused  ….(additional) four shift instructions  shr (op-code = 26) shift right by using value in (5-bit) c3 field shr R3, R4, 7 shift R4 right 7 times in to R3  shra (op-code = 27) Arithmetic shift right by using value in c3 field shra R3, R4, 7Ashift R4 right 7 times in to R3  shl (op-code = 28) shift left by using value in (5-bit) c3 field shl R8, R5, 6shift R5 left 6 times in to R8  shc (op-code = 29) shift left? circular by using value in c3 field shc R3, R4, 3shift R4 circular 3 times in to R3 Note: If count field contains 0, then these instructions will use the modified Type D format 4 count All use immediate addressing mode

Type D  four ALU instructions, plus others explained on following slides  add (op-code = 12) 2’s C register addition add R3, R5, R6 R[3] R[5] + R[6]  sub (op-code = 14) 2’s C register subtraction sub R3, R5, R6R[3] R[5] - R[6]  and (op-code = 20) logical AND operation between registers and R8, R3, R4R[8] R[3] & R[4]  or (op-code = 22) logical OR operation between registers or R8, R3, R4R[8] R[3] ~ R[4] register addressing mode Op-coderarb rc unused

Type D (modified form)  … four register based shift instructions, plus…  shr (op-code = 26) shift right by using value in register rc shr R3, R4, R5 shift R4 right in to R3 using number in R5  shra (op-code = 27) Arithmetic shift right by using register rc shra R3, R4, R5 Shift R4 right as above  shl (op-code = 28) shift left by using register rc shl R8, R5, R6 shift R5 left in to R8 using number in R6  shc (op-code = 29) shift circular by using register rc shc R3, R4, R6 shift R4 circular in to R3 using value in R6 Op-coderarb rc unused All use the register addressing mode

Type D (modified forms for branch instr )  … plus two branch instructions  br (op-code = 8) branch to address in rb depending on condition in rc (five possible conditions) brzr R3, R4 branch to address in R3 (if R4 == 0) brnz R3, R4 branch to address in R3 (if R4 ≠ 0) brpl R3, R4 branch to address in R3 (if R4 ≥ 0) brmi R3, R4 branch to address in R3 (if R4 < 0) br R3 branch to address in R3 (unconditional) Op-codeunusedrb rc unused cond

Type D (modified forms for branch instr )  brl (op-code = 9) branch to address in rb depending on condition in rc. Additionally, copy the PC in to ra before branching Op-coderarb rc unused cond Branch and link examples Function brlzr R1,R3, R4R[1] PC, then branch to address in R3 (if R4 == 0) brlnz R1,R3, R4R[1] PC, then branch to address in R3 (if R4 ≠ 0) brlpl R1,R3, R4R[1] PC, then branch to address in R3 (if R4≥ 0) brlmi R1,R3, R4R[1] PC, then branch to address in R3 (if R4 < 0) brl R1,R3R[1] PC, then ALWAYS branch to address in R3 brlnv R1R[1] PC, NEVER BRANCH

Condition Codes Op-codeunusedrb rc unused cond Mnemonicc3<2..0> Branch Condition brlnv000Link but never branch* br, brl001Unconditional branch brzr, brlzr010Branch if rc is zero brnz, brlnz011Branch if rc is not zero brpl, brlpl100Branch if rc is positive brmi, brlmi101Branch if rc is negative * “Branch never” i.e., brnv, does not exist

9301minus Table 2.6, page 58, text