Test and Characterization of a Variable-Capacity Multilevel DRAM VLSI Test Symposium May 1 - 5, 2005 John Koob, S. Ung, A. Rao, D. Leder, C. Joly, K. Breen,

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Presentation transcript:

Test and Characterization of a Variable-Capacity Multilevel DRAM VLSI Test Symposium May 1 - 5, 2005 John Koob, S. Ung, A. Rao, D. Leder, C. Joly, K. Breen, T. Brandon, M. Hume, B. Cockburn, D. Elliott VLSI Design Laboratory University of Alberta Edmonton, Canada 17/2/2005 v3.2

Outline Motivation MLDRAM Overview MLDRAM Fault Model Basic Functional Test Cell Voltage Drift Test Multilevel March Test Bitline Coupling Test Cell Plate Bump Test

Motivation Source: Computer Architecture: A Quantitative Approach, Hennessy and Patterson, 2003

DRAM vs. MLDRAM

Possible Storage Encoding Scheme 6 signal levels 5 binary bits are encoded from 2 cells 2.5 bits/cell on average

Read Operation in 4-Level MLDRAM Reference Generation (1)Reference Generation (2)Access Data & Reference CellsCopy Signal and Parallel SenseRestore Accessed Data Cells

Multilevel DRAM Fault Model Fault types: –SAF0/SAF1 - involves single code bit –SAF-random - several causes –SCF - interdependence among code bits –data retention fault –degraded noise margins Source: Redeker, et al, “Fault Modeling and Pattern-Sensitivity Testing for a Multilevel DRAM,” MTDT, July 2002, pp

Basic Functional Test Results 1. Write data level to base cell B 2. Write contrasting levels to N1 & N2 3. Read cell B and verify

Cell Voltage Drift Test 1. Write highest signal level to a set of cells 2. Wait for a predefined drift time 3. Test drift using page-mode read Graphical analysis using drift bitmaps: –new way to monitor cell drift –detects stuck bits, bitlines and wordlines –detects sense amplifier offsets

Cell Drift Test Results Predominant Thermometer Code

Multilevel March Test A 12n march test for six-level MLDRAM (using 5-digit thermometer codes):  {w00000}  {r00000, w00001}  {r00001, w00011}  {r00011, w00111}  {r00111, w01111}  {r01111, w11111}  {r11111} 100% cell yields (four-level, 55-fF cell)

Inter-Bitline Coupling Test

Bump Test Nominal curve is centered between two references DUT circuit to control back-bias

Multilevel Bump Test Curves are from bump tests for each level Nominal references: 0.3V, 0.9V, 1.5V Lowest noise margin: sensing 111

Conclusions MLDRAM success depends on effective characterization and testing 100% cell yield for 55-fF cells in 4-level mode Future test chips need a DRAM process Industrial partners are welcome Could fix the DRAM-disk access time gap by: Increasing capacity vs. DRAMs Sacrificing performance to improve cost per bit Revisiting the extended storage hierarchy stage