A high speed 10 to 12 bits pipe line ADC, design proposal for ECAL

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Presentation transcript:

A high speed 10 to 12 bits pipe line ADC, design proposal for ECAL D. DZAHINI, O.ROSSETTO, E. LAGORIO, J. BOUVIER, L. G-Martell H. GHAZLANE: CNESTEN Rabat, Maroc D. DALLET: IXL, Bordeaux Pipe line converters: Recall First prototype: results Second prototype: simulations Very next future and: perspectives Daniel DZAHINI - LPSC - Grenoble

High speed ADC: overview If one needs >10bits @ >10Mhz then choose pipe line architecture Daniel DZAHINI - LPSC - Grenoble

Daniel DZAHINI - LPSC - Grenoble The key points DAC, and amplifier allow reduction of number and offset of comparators. Redundancy (overlap Bits) allows digital correction. Pipelining decouples conversion rate from conversion time. Amplification errors are still a challenge. Daniel DZAHINI - LPSC - Grenoble

Diff amplifier Bode diagram, with 3pF,@ 2.7mW phase gain Daniel DZAHINI - LPSC - Grenoble

First prototype: 12 Bits ADC full schematic Total DC power consumption, without the S/H = 27mW @16MS/s This ratio of 1.7mW/Mhz@12bits is not too bad for a 3.5V process: Daniel DZAHINI - LPSC - Grenoble

Daniel DZAHINI - LPSC - Grenoble FULL LAYOUT FOR A 12 bits ADC, submitted in April 06 (the S/H was not included) Daniel DZAHINI - LPSC - Grenoble

First prototype: ADC 10bits basic features extended to 12bits Daniel DZAHINI - LPSC - Grenoble

Daniel DZAHINI - LPSC - Grenoble ADC testing board Daniel DZAHINI - LPSC - Grenoble

Daniel DZAHINI - LPSC - Grenoble Testing results 1 The DC power consumption is exactly fitting with our simulations: 27mW per ADC and 3mW for the common Bias stages The sampling speed is up to 15Mhz. The very fast power pulsing 100-200nS, at a ratio better than 1/1000. No Obvious missing code. Daniel DZAHINI - LPSC - Grenoble

Daniel DZAHINI - LPSC - Grenoble Testing results 2 Bias pulsing Daniel DZAHINI - LPSC - Grenoble

INL results with an input ramp Daniel DZAHINI - LPSC - Grenoble

Daniel DZAHINI - LPSC - Grenoble INL results with an input ramp => ENOB  9.5 bits !! Instead of 10 !! Daniel DZAHINI - LPSC - Grenoble

Improved SH for the 2nd prototype Non linearity simulations @ 25 Mhz Daniel DZAHINI - LPSC - Grenoble

Improved Sample & Hold simulations -Settling time -Accuracy fo 12bits (<250µV) -Linearity This means better than 30Mhz Daniel DZAHINI - LPSC - Grenoble

2nd prototype Submitted in January 07 Thru 12 bits including a S/H Speed: Beyond 30MHz Power: 35mW with fast and efficient standby command Daniel DZAHINI - LPSC - Grenoble

NEXT steps for the “12” bits ADC design Test of the 2nd 12 bits including a S/H Design of an interleaved 12 bits =>60MHz Optimization of the power dissipation with digital gain calibration Research for a 14 to 16bits ADC 60Mhz: if thesis Daniel DZAHINI - LPSC - Grenoble