Catalog RTOS Apps April 13, 2015 AM437x DDRless Changes for building Applications on QSPI XIP and/or L3 PRELIMINARY*** Catalog RTOS Apps April 13, 2015

Setup AM437X IDK EVM (http://www.ti.com/tool/tmdxidk437x) Software ARM Cortex-A9 MPU, up to 1000 MHz 32KB L1 Instruction cache and 32KB L1 data cache 256KB L2 cache or L3 RAM, 256KB OCMC RAM 32-bit DDR interface. QSPI interface to 64MB NOR. Up to 48MHz Software Sysbios Industrial SDK 2.1.1.2 XDC 3.31.1.33_core TI-RTOS 6.41.4.54 GNU v4.8.4 (Linaro) Application EtherCAT slave (Full Feature) + Motor control

EtherCAT slave + Motor setup Test setup information For steps on how to connect the board to the motor, and how to configure TwinCAT please refer to: http://processors.wiki.ti.com/index.php/SYSBIOS_Industrial_SDK_02.01.01_User_Guide#EtherCAT Building EtherCAT full feature: http://processors.wiki.ti.com/index.php/SYSBIOS_Industrial_SDK_02.01.01_User_Guide#Building_Full_Feature_EtherCAT_Application TwinCAT was used as EtherCAT master

Test Environment AM437x: A9 @ 600MHz DDR @ 400MHz QSPI @ 48MHz Motor Control and TwinCAT3 setup as guided at http://processors.wiki.ti.com/index.php/PRU_ICSS_EtherCAT Build Options: Complier flags: -mcpu=cortex-a9 -mtune=cortex-a9 -marm -mfloat-abi=hard -mfpu=neon -Dam4379 -DAM43XX_FAMILY_BUILD -DNO_UART_MSG_APP -O2 -g -gstrict-dwarf –Wall Linker flags: -mfloat-abi=hard -Dam4379 -DAM43XX_FAMILY_BUILD -DNO_UART_MSG_APP -O2 -g -gstrict-dwarf -Wall -Wl,-Map,"ecat_appl.map" -nostartfiles -static -Wl,--gc-sections -Wl,--defsym,STACKSIZE=0x18000 -Wl,--defsym,HEAPSIZE=0x400

Application EtherCAT slave + Motor control

DDRless build - Platform definition QSPI L3

DDR build - Platform definition

CCS configuration file changes for building Application on DDR or L3 or QSPI DDR build test Cache.configureL2Sram = false; Program.linkTemplate = java.lang.System.getenv("IA_SDK_HOME") + "/protocols/ethercat_slave/ecat_appl/ecat_appl.xdt"; Program.sectMap[".c_int00"].loadAddress = 0x80000000; L3 build test Cache.configureL2Sram = true; Program.sectMap[".c_int00"].loadAddress = 0x40500000; QSPI build test Program.linkTemplate = java.lang.System.getenv("IA_SDK_HOME") + "/protocols/ethercat_slave/ecat_appl/backup_xdt/ecat_appl_modif_QSPI_XIP.xdt“ Program.sectMap[".c_int00"].loadAddress = 0x30080000;

EtherCAT slave application changes for QSPI build NOR memory MMU attributes changed to Bufferable File: ecat_app_cnfg.h {(void *)0x30000000, SYS_MMU_CACHEABLE | SYS_MMU_BUFFERABLE}, //NOR - Cacheable - bufferable {(void *)0x30100000, SYS_MMU_CACHEABLE | SYS_MMU_BUFFERABLE}, //NOR - Cacheable - bufferable {(void *)0x30200000, SYS_MMU_CACHEABLE | SYS_MMU_BUFFERABLE}, //NOR - Cacheable - bufferable {(void *)0x30300000, SYS_MMU_CACHEABLE | SYS_MMU_BUFFERABLE}, //NOR - Cacheable - bufferable Board init change: File: tiescutils.c #ifndef XIP_QSPI board_init(BOARD_LED_DIGOUT | BOARD_TRICOLOR0_GREEN | BOARD_TRICOLOR1_RED | BOARD_HVS_DIGIN | BOARD_FLASH_MEMORY); #else BOARD_HVS_DIGIN); #endif Moving critical .text sections from NOR (REGION_TEXT) to OCMC (REGION_DATA)) in .xdt file Background info: http://processors.wiki.ti.com/index.php/SYS/BIOS_FAQs#3_Placing_SYS.2 text : { ...*(EXCLUDE_FILE(knl_*.o) .text.ti_sysbios_knl*) *(EXCLUDE_FILE(*Hwi*.o) .text.ti_sysbios*_Hwi*) ..... } > REGION_TEXT .data : {…. *(.text.ti_sysbios_knl*) *(.text.ti_sysbios*_Hwi*) …..} > REGION_DATA AT> REGION_TEXT

Example of automatic created Linker.cmd for QSPI XIP build - Memory regions allocation for QSPI build MEMORY { OCMCRAM (RWX) : org = 0x40300000, len = 0x20000 L2SRAM (RWX) : org = 0x40500000, len = 0x40000 NOR_MEM (RWX) : org = 0x30080000, len = 0x3f7ffff } REGION_ALIAS("REGION_BSS", OCMCRAM); REGION_ALIAS("REGION_TEXT", NOR_MEM); REGION_ALIAS("REGION_DATA", OCMCRAM); REGION_ALIAS("REGION_STACK", OCMCRAM); REGION_ALIAS("REGION_HEAP", OCMCRAM); REGION_ALIAS("REGION_ARM_EXTAB", OCMCRAM); REGION_ALIAS("REGION_ARM_EXIDX", OCMCRAM); Application binary size: 231KB

Bootloader changes QSPI build L3 build Fixing point of entrance to NOR. Note: Avoiding image copy, then we won’t need to add TI’s binary header when converting .out to .bin. File: sbl_qspi.c #ifdef XIP_QSPI         *pEntryPoint = 0x30080000;  //Fixed QSPI XIP          CONSOLEUtilsPrintf("\nChanging entry point to %x\n",pEntryPoint);  #else          status = SblQspiImageCopy(pEntryPoint);  #endif L3 build Enabling L2 as SRAM File: sbl_am43xx_platform.c HW_WR_REG32((0x44E10654), 4); HW_WR_REG32((0x44E101E0), 0x10000);

Optional Steps: If flashing QSPI using SD card Copy sysbios_ind_sdk_prebuilt_02_01_01_02\bootloaders\AM437X_IDK\mmcsd_release\MLO to SD card Copy C:\TI\sysbios_ind_sdk_2.1.1.2\sdk\starterware\binary\qspi_app_flash_writer\bin\am43xx- evm\gcc\qspi_app_flash_writer_a9host_release_ti.bin and renamed as app Copy previously modified bootloader from C:\TI\sysbios_ind_sdk_2.1.1.2\sdk\starterware\binary\bootloader\bin\am43xx-evm\ccs \bootloader_boot_qspi_a9host_release.bin and renamed as boot Convert .out in a .bin using below command: arm-none-eabi-objcopy.exe -O binary -R .ARM.exidx -R .debug_aranges -R .debug_info -R .debug_abbrev -R .debug_line -R .debug_frame -R .debug_str -R .debug_loc -R .debug_ranges ecat_appl.out ecat_appl.bin Note: arm-none-eabi-objcopy.exe can be found at C:\TI\ccsv6\tools\compiler\gcc-arm-none-eabi-4_8-2014q3\bin Copy C:\TI\sysbios_ind_sdk_2.1.1.2\sdk\protocols\ethercat_slave\ecat_appl\am437x_release\ ecat_appl.bin and renamed as image Created a text file with name config (without file extension) and added contents boot 0x0 image 0x80000 Insert SD card and turn on the board. Wait few seconds or check UART messages for “Flashing completed” Removed the SD card and boot the board. Wait for ~20 seconds and ECAT application should start!. LEDs turn on.