Melinda Wong 1, Jesus del Alamo 1, Akira Inoue 2, Takayuki Hisaka 2, and Kazuo Hayashi 2 1 Massachusetts Institute of Technology, Microsystems Technology Laboratory, Cambridge, MA (USA), 2 Mitsubishi Electric, Itami, Hyogo, Japan Impact of Drain Recess Length on the RF performance of GaAs PHEMTs Experimental. Experimental. Tune impedances for P OUT at the 3-dB compression point while maintaining G T = 15 dB (left) 2 – 18 GHz Maury Microwave automated tuner system Study P OUT dependence on L RD Perform complete characterizations of different L RD devices Load pull measurements carried out at MIT (right) Fig. 4: Typical RF power measurement. Fig. 3: MIT load pull station setup Introduction Goal: Increase the output power of GaAs PHEMT – Approach: Increase gate-drain recess length (L RD ) Good for power: L RD  BV DG  V DS  P OUT  Bad for power: L RD  R D  P OUT  Published results: L RD  P OUT  Introduction Goal: Increase the output power of GaAs PHEMT – Approach: Increase gate-drain recess length (L RD ) Good for power: L RD  BV DG  V DS  P OUT  Bad for power: L RD  R D  P OUT  Published results: L RD  P OUT  Fig. 2: BV DG and R D versus L RD.Fig. 1: Schematic of GaAs PHEMT under study. L g = 0.25 um. Power Sweep Fig. 5: Gain and PAE versus P OUT at V DD = 5 V, I D0 = 100 mA/mm at 16 GHz. Fig. 6: I D and I G versus P OUT at V DD = 5 V, I D0 = 100 mA/mm at 16 GHz. As L RD  : –Gain compresses earlier –PAE at 3-dB compression  –Self-bias  –I G at 3-dB compression  Impact of Operating Voltage V DD [V] I D0 = 100 mA/mm Fig. 7: P OUT,3-dB versus V DD at 10 GHz and I D0 = 100 mA/mm. Fig. 8: P OUT,3-dB versus V DD at 16 GHz with I D0 = 100 mA/mm. Freq = 10 GHz: P OUT,3-dB highest for L RD = 0.7 um device Freq = 16 GHz: P OUT,3-dB highest for L RD = 0.5 um device –At sufficiently high V DD, longer L RD devices can no longer sustain G T = 15 dB V DD [V] I D0 = 100 mA/mm Load Line Analysis Fig. 9: Ideal load line for maximum P OUT under Class A operation. Device loading condition controls the slope of the load line (left) Maximum P OUT given by: Fig. 10: Load lines for devices with different L RD. Load lines become shallower as L RD increases (right) - Not advantageous from a power standpoint - Due to 15 dB “gain” restriction To keep G T constant: L RD  g m  R L  Freq = 16 GHz Bias: V DS = 4 V, I D = 100 mA/mm. I D [mA/mm] V DS [V] L RD  V GS = 0.6 V Effect of Drain Recess Length on DC Characteristics Fig. 11: Output characteristics of devices with different L RD. V DS : 0 – 4 V, V GS : –0.8 to 0.6 V in 0.2 V increments. I D [mA/mm] V DS [V] L RD Table 1: DC characteristics of devices with different L RD. As L RD  : –V DS,SAT  –I MAX  –g m  –f T,peak  P OUT is reduced V GS = 0.6 V V GS = 0 V Delay Time Analysis Fig. 12: f T versus V DD and I D = 100 mA/mm. Fig. 13: Intrinsic delay versus V DD. f T [GHz] V DD [V] L RD = 0.3 um L RD = 0.5 um L RD = 0.7 um L RD = 0.9 um gatetr,  drain  V DD [V] L RD = 0.3 um L RD = 0.5 um L RD = 0.7 um L RD = 0.9 um Intrinsic delay [ps] L RD  f T  Why? – is the transit of electrons across the gate – is the drain delay due to the extension of the depletion region toward the extrinsic drain [1] L RD   Conclusions An optimum L RD : – Must be chosen to achieve the highest P OUT possible – Is reduced as operating frequency increases As L RD  : – Earlier and softer compression – Load lines become increasingly shallow – I MAX  – g m  – f T   due to the extension of the depletion region References [1] T. Suemitsu, EDL, 2004.