Melinda Wong 1, Jesus del Alamo 1, Akira Inoue 2, Takayuki Hisaka 2, and Kazuo Hayashi 2 1 Massachusetts Institute of Technology, Microsystems Technology.

Slides:



Advertisements
Similar presentations
Transistors (MOSFETs)
Advertisements

Physical structure of a n-channel device:
High efficiency Power amplifier design for mm-Wave
The High Voltage/High Power FET (HiVP)
1/42 Changkun Park Title Dual mode RF CMOS Power Amplifier with transformer for polar transmitters March. 26, 2007 Changkun Park Wave Embedded Integrated.
Transistors These are three terminal devices, where the current or voltage at one terminal, the input terminal, controls the flow of current between the.
Lecture #26 Gate delays, MOS logic
Distributed Power Amplifiers-Output Power and Efficiency Considerations Prasad N. Shastry (S. N. Prasad) 1, Senior Member, IEEE, and Amir S. Ibrahim 2.
Highly Linear Power Amplifiers for Broadband Wireless Applications Power Amplifiers for Wireless Communications Workshop September 9, 2002 M. Siddiqui,
Characterization of two Field-Plated GaN HEMT Structures
Fig. 5.1 Physical structure of the enhancement-type NMOS transistor: (a) perspective view; (b) cross section. Typically L = 1 to 10 m, W = 2 to 500.
Slide 19/3/2002 S. Xie, V. Paidi, R. Coffie, S. Keller, S. Heikman, A. Chini, U. Mishra, S. Long, M. Rodwell Department of Electrical and Computer Engineering,
1 Scalable E-mode N-polar GaN MISFET devices and process with self-aligned source/drain regrowth Uttam Singisetti*, Man Hoi Wong, Sansaptak Dasgupta, Nidhi,
Week 9a OUTLINE MOSFET ID vs. VGS characteristic
Electronics Principles & Applications Sixth Edition Chapter 7 More About Small-Signal Amplifiers (student version) ©2003 Glencoe/McGraw-Hill Charles A.
LECTURE 4. HIGH-EFFICIENCY POWER AMPLIFIER DESIGN
1 Mobile Phone Testing using Impedance Tuners Roman Meierer and Steve Dudkiewicz Your Complete Measurement & Modeling Solutions Partner.
Microwave Amplifier Design
Semiconductor Devices III Physics 355. Transistors in CPUs Moore’s Law (1965): the number of components in an integrated circuit will double every year;
Junction Field Effect Transistor
FET ( Field Effect Transistor)
McGraw-Hill © 2008 The McGraw-Hill Companies Inc. All rights reserved. Electronics Principles & Applications Seventh Edition Chapter 7 More About Small-Signal.
Microwave Engineering, 3rd Edition by David M. Pozar
Seoul National University CMOS for Power Device CMOS for Power Device 전파공학 연구실 노 영 우 Microwave Device Term Project.
© 2013 The McGraw-Hill Companies, Inc. All rights reserved. McGraw-Hill 5-1 Electronics Principles & Applications Eighth Edition Chapter 5 Transistors.
Avalanche Transit Time Devices
Chapter 11 Field effect Transistors: Operation, Circuit, Models, and Applications Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction.
ECE 340 ELECTRONICS I MOS APPLICATIONS AND BIASING.
1 An Introduction to Gallium Nitride (GaN) Device Characterization Steve Dudkiewicz, Eng Your Complete Measurement & Modeling Solutions Partner.
Electronic Devices Laboratory CE/EE 3110 Low Frequency Characteristics of Junction Field Effect Transistors Low Frequency Characteristics.
Device Characterization ECE/ChE 4752: Microelectronics Processing Laboratory Gary S. May April 1, 2004.
Network Analyzers From Small Signal To Large Signal Measurements
A NEW METHOD TO STABILIZE HIGH FREQUENCY HIGH GAIN CMOS LNA RF Communications Systems-on-chip Primavera 2007 Pierpaolo Passarelli.
ECE 342 – Jose Schutt-Aine 1 ECE 342 Solid-State Devices & Circuits 16. Active Loads Jose E. Schutt-Aine Electrical & Computer Engineering University of.
1 Microwave Semiconductor Devices Major Applications Substrate Material Frequency Limitation Device Transmitters AmplifiersSi, GaAs, InP< 300 GHzIMPATT.
1 High Frequency Model of Sub-100nm High-k RF CMOS ○M. Nakagawa 1, J.Song 1, Y. Nara 2, M. Yasuhira 2 *, F. Ohtsuka 2, T. Arikado 2 **, K. Nakamura 2,
Amplifiers Amplifier Parameters Gain = Po/Pi in dB = 10 log (Po/Pi)
© 2000 Prentice Hall Inc. Figure 5.1 n-Channel enhancement MOSFET showing channel length L and channel width W.
Introduction LNA Design figure of merits: operating power consumption, power gain, supply voltage level, noise figure, stability (Kf & B1f), linearity.
7-1 McGraw-Hill © 2013 The McGraw-Hill Companies, Inc. All rights reserved. Electronics Principles & Applications Eighth Edition Chapter 7 More About Small-Signal.
ANALOGUE ELECTRONICS CIRCUITS 1
11. 9/14 Music for your ears 9/14 Musique 101 9/14 Audio Spectrum 4.
© 2013 The McGraw-Hill Companies, Inc. All rights reserved. McGraw-Hill 7-1 Electronics Principles & Applications Eighth Edition Chapter 7 More About Small-Signal.
MOSFET Current Voltage Characteristics Consider the cross-sectional view of an n-channel MOSFET operating in linear mode (picture below) We assume the.
1 DMT 121 – ELECTRONIC DEVICES CHAPTER 5: FIELD-EFFECT TRANSISTOR (FET)
Electronics Principles & Applications Fifth Edition Chapter 7 More About Small-Signal Amplifiers ©1999 Glencoe/McGraw-Hill Charles A. Schuler.
DOUBLE-GATE DEVICES AND ANALYSIS 발표자 : 이주용
The MOS capacitor. (a) Physical structure of an n+-Si/SiO2/p-Si MOS capacitor, and (b) cross section (c) The energy band diagram under charge neutrality.
VI. HIGH-EFFICIENCY SWITCHMODE HYBRID AND MMIC POWER AMPLIFIERS:
Electronics Technology Fundamentals Chapter 21 Field-Effect Transistors and Circuits.
1 MOS Field-Effect Transistors (MOSFETs). Copyright  2004 by Oxford University Press, Inc. Microelectronic Circuits - Fifth Edition Sedra/Smith2 Figure.
Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display. MALVINO & BATES SEVENTH EDITION Electronic PRINCIPLES.
CHAPTER 4 :JFET Junction Field Effect Transistor.
FET ( Field Effect Transistor) 1.Unipolar device i. e. operation depends on only one type of charge carriers (h or e) 2.Voltage controlled.
MOS Capacitor Lecture #5. Transistor Voltage controlled switch or amplifier : control the output by the input to achieve switch or amplifier Two types.
Lets Design an LNA! Anurag Nigam.
Day 2 I_DC RFin RFout Bias De-coupling Circuit Lab5: Device Biasing.
Variable Gain CMOS LNA MOREIRA E SILVA, Paulo Marcio, DE SOUSA, Fernando Rangel Introduction Simulation.
Field effect Transistors: Operation, Circuit, Models, and Applications
Recall-Lecture 4 Current generated due to two main factors
Notes on Diodes 1. Diode saturation current:  
Week 9a OUTLINE MOSFET ID vs. VGS characteristic
Yufei Wu, Jesús A. del Alamo
Review of semiconductor physics
Load-Pull Measurements
The MOS Transistors, n-well
Week 9a OUTLINE MOSFET ID vs. VGS characteristic
Lecture #17 (cont’d from #16)
Fig. 3 Electrical characterization and TCAD simulations of 1D2D-FET.
Dr. Hari Kishore Kakarla ECE
Presentation transcript:

Melinda Wong 1, Jesus del Alamo 1, Akira Inoue 2, Takayuki Hisaka 2, and Kazuo Hayashi 2 1 Massachusetts Institute of Technology, Microsystems Technology Laboratory, Cambridge, MA (USA), 2 Mitsubishi Electric, Itami, Hyogo, Japan Impact of Drain Recess Length on the RF performance of GaAs PHEMTs Experimental. Experimental. Tune impedances for P OUT at the 3-dB compression point while maintaining G T = 15 dB (left) 2 – 18 GHz Maury Microwave automated tuner system Study P OUT dependence on L RD Perform complete characterizations of different L RD devices Load pull measurements carried out at MIT (right) Fig. 4: Typical RF power measurement. Fig. 3: MIT load pull station setup Introduction Goal: Increase the output power of GaAs PHEMT – Approach: Increase gate-drain recess length (L RD ) Good for power: L RD  BV DG  V DS  P OUT  Bad for power: L RD  R D  P OUT  Published results: L RD  P OUT  Introduction Goal: Increase the output power of GaAs PHEMT – Approach: Increase gate-drain recess length (L RD ) Good for power: L RD  BV DG  V DS  P OUT  Bad for power: L RD  R D  P OUT  Published results: L RD  P OUT  Fig. 2: BV DG and R D versus L RD.Fig. 1: Schematic of GaAs PHEMT under study. L g = 0.25 um. Power Sweep Fig. 5: Gain and PAE versus P OUT at V DD = 5 V, I D0 = 100 mA/mm at 16 GHz. Fig. 6: I D and I G versus P OUT at V DD = 5 V, I D0 = 100 mA/mm at 16 GHz. As L RD  : –Gain compresses earlier –PAE at 3-dB compression  –Self-bias  –I G at 3-dB compression  Impact of Operating Voltage V DD [V] I D0 = 100 mA/mm Fig. 7: P OUT,3-dB versus V DD at 10 GHz and I D0 = 100 mA/mm. Fig. 8: P OUT,3-dB versus V DD at 16 GHz with I D0 = 100 mA/mm. Freq = 10 GHz: P OUT,3-dB highest for L RD = 0.7 um device Freq = 16 GHz: P OUT,3-dB highest for L RD = 0.5 um device –At sufficiently high V DD, longer L RD devices can no longer sustain G T = 15 dB V DD [V] I D0 = 100 mA/mm Load Line Analysis Fig. 9: Ideal load line for maximum P OUT under Class A operation. Device loading condition controls the slope of the load line (left) Maximum P OUT given by: Fig. 10: Load lines for devices with different L RD. Load lines become shallower as L RD increases (right) - Not advantageous from a power standpoint - Due to 15 dB “gain” restriction To keep G T constant: L RD  g m  R L  Freq = 16 GHz Bias: V DS = 4 V, I D = 100 mA/mm. I D [mA/mm] V DS [V] L RD  V GS = 0.6 V Effect of Drain Recess Length on DC Characteristics Fig. 11: Output characteristics of devices with different L RD. V DS : 0 – 4 V, V GS : –0.8 to 0.6 V in 0.2 V increments. I D [mA/mm] V DS [V] L RD Table 1: DC characteristics of devices with different L RD. As L RD  : –V DS,SAT  –I MAX  –g m  –f T,peak  P OUT is reduced V GS = 0.6 V V GS = 0 V Delay Time Analysis Fig. 12: f T versus V DD and I D = 100 mA/mm. Fig. 13: Intrinsic delay versus V DD. f T [GHz] V DD [V] L RD = 0.3 um L RD = 0.5 um L RD = 0.7 um L RD = 0.9 um gatetr,  drain  V DD [V] L RD = 0.3 um L RD = 0.5 um L RD = 0.7 um L RD = 0.9 um Intrinsic delay [ps] L RD  f T  Why? – is the transit of electrons across the gate – is the drain delay due to the extension of the depletion region toward the extrinsic drain [1] L RD   Conclusions An optimum L RD : – Must be chosen to achieve the highest P OUT possible – Is reduced as operating frequency increases As L RD  : – Earlier and softer compression – Load lines become increasingly shallow – I MAX  – g m  – f T   due to the extension of the depletion region References [1] T. Suemitsu, EDL, 2004.