CSE477 L05 IC Manufacturing.1Irwin&Vijay, PSU, 2003 CSE477 VLSI Digital Circuits Fall 2003 Lecture 05: IC Manufacturing Mary Jane Irwin ( ) Guest Lecturer: Greg Link [Adapted from Rabaey’s Digital Integrated Circuits, Second Edition, ©2003 J. Rabaey, A. Chandrakasan, B. Nikolic]

CSE477 L05 IC Manufacturing.2Irwin&Vijay, PSU, 2003 Review: CMOS Inverter V DD V out CLCL V in  Full rail-to-rail swing  high noise margins  Low output impedance  High input impedance  No direct path steady-state between power and ground  no static power dissipation  Propagation delay a function of load capacitance and on resistance of transistors

CSE477 L05 IC Manufacturing.3Irwin&Vijay, PSU, 2003 The Manufacturing Process For a great tour (that doesn’t work anymore!!!) through the IC manufacturing process and its different steps, check out html

CSE477 L05 IC Manufacturing.4Irwin&Vijay, PSU, 2003 Growing the Silicon Ingot From Smithsonian, 2000

CSE477 L05 IC Manufacturing.5Irwin&Vijay, PSU, 2003 CMOS Process at a Glance Define active areas Etch and fill trenches Implant well regions Deposit and pattern polysilicon layer Implant source and drain regions and substrate contacts Create contact and via windows Deposit and pattern metal layers  One full photolithography sequence per layer (mask)  Built (roughly) from the bottom up 5 metal 2 4 metal 1 2 polysilicon 3 source and drain diffusions 1 tubs (aka wells, active areas) exception!

CSE477 L05 IC Manufacturing.6Irwin&Vijay, PSU, 2003 oxidation optical mask process step photoresist coating photoresist removal (ashing) spin, rinse, dry acid etch photoresist development stepper exposure Photolithographic Process

CSE477 L05 IC Manufacturing.7Irwin&Vijay, PSU, 2003 Patterning - Photolithography 1.Oxidation 2.Photoresist (PR) coating 3.Stepper exposure 4.Photoresist development and bake 5.Acid etching Unexposed (negative PR) Exposed (positive PR) 6.Spin, rinse, and dry 7.Processing step Ion implantation Plasma etching Metal deposition 8.Photoresist removal (ashing) mask SiO 2 PR UV light

CSE477 L05 IC Manufacturing.8Irwin&Vijay, PSU, 2003 Example of Patterning of SiO2 Si-substrate Silicon base material 1&2. After oxidation and deposition of negative photoresist Photoresist SiO 2 Si-substrate SiO 2 8. Final result after removal of resist Si-substrate SiO 2 5. After etching Hardened resist SiO 2 Si-substrate 4. After development and etching of resist, chemical or plasma etch of SiO 2 Hardened resist Chemical or plasma etch

CSE477 L05 IC Manufacturing.9Irwin&Vijay, PSU, 2003 Diffusion and Ion Implantation 1.Area to be doped is exposed (photolithography) 2.Diffusion or Ion implantation

CSE477 L05 IC Manufacturing.10Irwin&Vijay, PSU, 2003 Deposition and Etching 1.Pattern masking (photolithography) 2.Deposit material over entire wafer CVD (Si 3 N 4 ) chemical deposition (polysilicon) sputtering (Al) 3.Etch away unwanted material wet etching dry (plasma) etching

CSE477 L05 IC Manufacturing.11Irwin&Vijay, PSU, 2003 Planarization: Polishing the Wafers From Smithsonian, 2000

CSE477 L05 IC Manufacturing.12Irwin&Vijay, PSU, 2003 Self-Aligned Gates 1.Create thin oxide in the “active” regions, thick elsewhere 2.Deposit polysilicon 3.Etch thin oxide from active region (poly acts as a mask for the diffusion) 4.Implant dopant

CSE477 L05 IC Manufacturing.13Irwin&Vijay, PSU, 2003 Simplified CMOS Inverter Process cut line p well

CSE477 L05 IC Manufacturing.14Irwin&Vijay, PSU, 2003 P-Well Mask

CSE477 L05 IC Manufacturing.15Irwin&Vijay, PSU, 2003 Active Mask

CSE477 L05 IC Manufacturing.16Irwin&Vijay, PSU, 2003 Poly Mask

CSE477 L05 IC Manufacturing.17Irwin&Vijay, PSU, 2003 P+ Select Mask

CSE477 L05 IC Manufacturing.18Irwin&Vijay, PSU, 2003 N+ Select Mask

CSE477 L05 IC Manufacturing.19Irwin&Vijay, PSU, 2003 Contact Mask

CSE477 L05 IC Manufacturing.20Irwin&Vijay, PSU, 2003 Metal Mask

CSE477 L05 IC Manufacturing.21Irwin&Vijay, PSU, 2003 A Modern CMOS Process p- p-epi p welln well p+n+ gate oxide Al (Cu) tungsten SiO 2 TiSi 2 Dual-Well Trench-Isolated CMOS field oxide

CSE477 L05 IC Manufacturing.22Irwin&Vijay, PSU, 2003 Modern CMOS Process Walk-Through p + p-epi Base material: p+ substrate with p-epi layer p+ After plasma etch of insulating trenches using the inverse of the active area mask p + p-epi SiO 2 3 SiN 4 After deposition of gate-oxide and sacrifical nitride (acts as a buffer layer)

CSE477 L05 IC Manufacturing.23Irwin&Vijay, PSU, 2003 CMOS Process Walk-Through, con’t SiO 2 After trench filling, CMP planarization, and removal of sacrificial nitride After n-well and V Tp adjust implants n After p-well and V Tn adjust implants p

CSE477 L05 IC Manufacturing.24Irwin&Vijay, PSU, 2003 CMOS Process Walk-Through, con’t After polysilicon deposition and etch poly(silicon) After n+ source/dram and p+ source/drain implants. These steps also dope the polysilicon. p + n+

CSE477 L05 IC Manufacturing.25Irwin&Vijay, PSU, 2003 CMOS Process Walk-Through, con’t

CSE477 L05 IC Manufacturing.26Irwin&Vijay, PSU, 2003 Layout Editor: max Design Frame

CSE477 L05 IC Manufacturing.27Irwin&Vijay, PSU, 2003 max Layer Representation  Metals (five) and vias/contacts between the interconnect levels l Note that m5 connects only to m4, m4 only to m3, etc., and m1 only to poly, ndif, and pdif l Some technologies support “stacked vias”  Wells (nw) and other select areas (pplus, nplus, prb)  Active – active areas on/in substrate (poly gates, transistor channels (nfet, pfet), source and drain diffusions (ndif, pdif), and well contacts (nwc, pwc))

CSE477 L05 IC Manufacturing.28Irwin&Vijay, PSU, 2003 CMOS Inverter max Layout V DD GND NMOS (2/.24 = 8/1) PMOS (4/.24 = 16/1) metal2 metal1 polysilicon In Out metal1-poly via metal2-metal1 via metal1-diff via pfet nfet pdif ndif

CSE477 L05 IC Manufacturing.29Irwin&Vijay, PSU, 2003 Simplified Layouts in max  Online design rule checking (DRC)  Automatic fet generation (just overlap poly and diffusion and it creates a transistor)  Simplified via/contact generation l v12, v23, v34, v45 l ct, nwc, pwc 0.44 x 0.44 m1 0.3 x 0.3 ct 0.44 x 0.44 poly

CSE477 L05 IC Manufacturing.30Irwin&Vijay, PSU, 2003 Design Rule Checker poly_not_fet to all_diff minimum spacing = 0.14 um

CSE477 L05 IC Manufacturing.31Irwin&Vijay, PSU, 2003 Design Rules  Interface between the circuit designer and process engineer  Guidelines for constructing process masks  Unit dimension: minimum line width l scalable design rules: lambda parameter l absolute dimensions: micron rules  Rules constructed to ensure that design works even when small fab errors (within some tolerance) occur  A complete set includes l set of layers l intra-layer: relations between objects in the same layer l inter-layer: relations between objects on different layers

CSE477 L05 IC Manufacturing.32Irwin&Vijay, PSU, 2003 Why Have Design Rules?  To be able to tolerate some level of fabrication errors such as 1.Mask misalignment 2.Dust 3.Process parameters (e.g., lateral diffusion) 4.Rough surfaces

CSE477 L05 IC Manufacturing.33Irwin&Vijay, PSU, 2003 Intra-Layer Design Rule Origins  Minimum dimensions (e.g., widths) of objects on each layer to maintain that object after fab l minimum line width is set by the resolution of the patterning process (photolithography)  Minimum spaces between objects (that are not related) on the same layer to ensure they will not short after fab micron

CSE477 L05 IC Manufacturing.34Irwin&Vijay, PSU, 2003 Inter-Layer Design Rule Origins 1. Transistor rules – transistor formed by overlap of active and poly layers Transistors Catastrophic error Unrelated Poly & Diffusion Thinner diffusion, but still working

CSE477 L05 IC Manufacturing.35Irwin&Vijay, PSU, 2003 Transistor Layout

CSE477 L05 IC Manufacturing.36Irwin&Vijay, PSU, 2003 Inter-Layer Design Rule Origins, Con’t 2. Contact and via rules M1 contact to p-diffusion M1 contact to poly Mx contact to My Contact Mask Via Masks both materials mask misaligned M1 contact to n-diffusion Contact: 0.44 x 0.44

CSE477 L05 IC Manufacturing.37Irwin&Vijay, PSU, 2003 Next Lecture and Reminders  Next lecture l Static complementary CMOS gate design -Reading assignment – Rabaey, et al,  Reminders l HW2 due September xx th l Evening midterm exam scheduled -Monday, October 20 th, 20:15 to 22:15, Location TBD -Please let me know ASAP (via ) if you have a conflict –Only one midterm conflict filed for so far