1 High-Performance Schottky Barrier MOSFET Horng-Chih Lin Department of Electronics Engineering & Institute of Electronics National Chiao Tung University September 19, 2005

2 Outline Background Low  B Source Field-induced Drain (FID) Structure Non-Si Channel Materials Interface Modulation Techniques Summary

3 SB MOSFET Source Drain Silicide Substrate Gate Source/drain made of metallic material (e.g., silicide) in lieu of heavily doped semiconductor. First reported in 1968 by Lepselter and Sze ( Proc. of IEEE, p.1400 (1968)).

4 Easy processing Elimination of S/D implant Ultra-shallow and abrupt junction Low S/D sheet resistance Low process temperature Advantages of SB MOSFET

5 ITRS 2003

6 Device Intrinsic Speed I on :I off Ratio

7 Off-state (V G < V T ) On-state (V G > V T ) Potential Distribution IEEE ED, V-47, p.1241 (2000) Source Channel Drain

8 Major Issues (I)  bn On current, limited by (i)Barrier height - PtSi (  Bp = 0.24 eV) for pMOS - ErSi 2 (  Bn = 0.27 eV) for nMOS - Near-zero or negative  Bp desired (ii) Barrier width - Modulated by gate bias - Gate overlaps with source necessary

9 Major Issues (II)  bp Off current (i)Major Conduction mechanism: Field emission of holes (electrons) for nMOS (pMOS) at drain junction (ii) Structure Gate/drain overlap structure aggravates the leakage

10 Performance of Sub- 40 nm pMOS Appl. Phys. Lett., V-74, p.1174 (1999) n + poly: L = 27 nm; p + poly: L = 40 nm

11 25 nm p-Channel SOI SB MOSFET Jpn. J. Appl. Phys. (Part I), V-39, p.4757 (2000) PtSi source/drain and metal gate

12 Methods to Improve Performance Development of low  B S/D materials - Zero or even negative barrier height highly desired - Use of SOI with ultra-thin body to reduce the leakage Implementation of FID structure Use of non-Si channel materials - Exs. CNT and Ge (SiGe) channel Metal/channel interface modulation - Insertion of an ultra-thin dielectric layer - Dopant segregation

13 Outline Background Low  B Source Field-induced Drain (FID) Structure Non-Si Channel Materials Interface Modulation Techniques Summary

14 Barrier Height (eV) PtSi (1) PtSi (2) ErSi (1) TbSi (2) DySi (2) YbSi (2) ErSi (2) PMOS (hole) NMOS (electron) (1) IEDM Tech. Dig. p.57 (2000) (2) EDL., Vol.25, p.525 (2004) Barrier Height at Silicide/Si Junctions

15 Characteristics of Schottky Diodes EDL., Vol.25, p.525 (2004)

16 NMOS with YbSi 2-x S/D IEEE EDL., Vol.25, p.525 (2004)

17 VDVD Buried oxide VDVD SB MOSFETs Built on SOI with Ultra-thin body Significant portion of the leakage blocked by the buried oxide

18 SB MOSFET on Ultra-thin Body SOI IEDM ‘ 2000, p.57 SOI thickness ~ 10 nm

19 Outline Background Low  B S/D Field-induced Drain (FID) Structure Non-Si Channel Materials Interface Modulation Techniques Summary

20 Substrate Sub-gate Substrate Sub-gate SB MOSFETs with Field-induced Drain (FID) NSA structure SA structure

21 Substrate Sub-gate - Barrier width modulated by sub-gate bias - Source NOT necessary to overlap with the main-gate - Ambipolar operation capability

22 Fabrication Flow - Amorphous Si deposition (LPCVD, 550 o C, 50 nm) - Re-crystallization (in N 2, 600 o C, 24 hr) - Gate oxide (LPCVD, 20 nm) - Gate formation (n + poly-Si, 200 nm ) - CVD oxide (LPCVD, 200 nm) - Oxide patterning - Co salicide treatment

23 - Passivation (PECVD oxide, 550 nm) - Contact hole patterning - Metal pad and sub-gate formation Fabrication Flow (Cont.)

24 Sub-gate Reduction of Off-state Leakage by FID Source Drain V G << V th The FID expels the high- field region away from the drain junction. Field-emission leakage encountered in conventional SB devices thus suppressed.

25 Sub-gate Modulation of ON Current by FID Drain Source V G > V th Dashed line has higher sub-gate bias Tunneling barrier width modulated by the sub-gate bias. Depending on the polarity of applied bias, the device could be set for either n- or p-mode operation.

26 Conventional SB TFT FID SB TFT Ambipolar Poly-Si TFTs with FID H. C. Lin et al., IEDM’2000, p.857 V sub =-50V V D = -5V V G (V) - On/off current ratio < On/off current ratio ~ 10 6 V D = -5V V sub =50V V D = 5V

27 New Modified Characterization Scheme H. C. Lin et al., IEDM’2004, p I D (A) V G Step 1: Determination of V FB Step 3: Extract of DOS Step 2:  s as a function of V G The new method Incremental method FEC theory Only two simple I-V measurements at room temperature from a single device are all that needed for full band-gap DOS extraction

28 As-deposited SPC ELA Effect of Channel Crystallization SPC Channel, L/W = 1/20  m/  m

29 TEM Photos Grain size ~ 20 nm Grain size ~ 300 nm Grain size ~ 50 nm As-deposited poly-Si

30 SEM Fin width Channel length VSVS VGVG V G, sub Al sub-gate n + poly-Si gate CoSi 2 source CoSi 2 drain VDVD The top view of device structure SB FinFET

31 SS= 60.6 mV/dec SS=60.8 mV/dec.  V G,sub  = 7.5 V V D = 0.1 V V D = -0.1 V, L = 470 nm, Fin width = 50 nm V D = 1.5 V V D = -1.5 V Ambipolar Operation with Ideal Subthreshold Swing (IEEE NANO’02)

32 V G - V th = 0 ~ -1.2 V in steps of V V G - V th = 0 ~ -1.2 V in steps of V Impact of S/D Material IEEE EDL., Vol.24, p.102 (2003) L = 110 nm CoSi S/D PtSi S/D

33 CNT Devices with FID IEDM’2004 p. 687

34 CNT Devices with FID IEDM’2004 p. 687

35 Outline Background Low  B Source Field-induced Drain (FID) Structure Non-Si Channel Materials Interface Modulation Techniques Summary

36 SB MOSFET with SiGe Channel IEEE EDL Vol. 23, p. 460 (2002)

37 SB MOSFET with SiGe Channel IEEE EDL Vol. 23, p. 460 (2002)

38 Ge pMOSFETs With NiGe S/D IEEE EDL Vol. 26, p. 81 (2005) NiGe S/D Barrier height ~ 0.16 eV Drive current 5 times higher than Si PMOS with PtSi S/D

39 SB PMOS on GOI with GePt S/D IEEE EDL Vol. 26, Vol. 26, p. 102 (2005)

40  Bp of –0.05 eV was reported for CNT FET CNT FET with Negative Barrier Height Nature, Vol.424, p.654 (2003)

41 Background Low  B Source Field-induced Drain (FID) Structure Non-Si Channel Materials Interface Modulation Techniques Summary Outline

42 An ultrathin insulator at the interface trades a reduction in the thermionic for a tunneling barrier. The key is to reduce the thermionic barrier while limiting the tunneling barrier. The Si in the direct vicinity of the metal acquires a dipole moment due to the influence of metal-induced gap states, generating a barrier to electron injection. Reduction of Tunneling Resistance with an Ultrathin Interfacial Layer IEEE Trans. Nanotechnology, Vol.3 p.92 (2003)

43 Resistance drops sharply as gap states are blocked and the Fermi level is liberated. Reduction of Tunneling Resistance with an Ultrathin Interfacial Layer IEEE Trans. Nanotechnology, Vol.3 p.92 (2003)

44 Reduction of Tunneling Resistance with an Ultrathin Interfacial Layer IEEE Trans. Nanotechnology, Vol.3 p.92 (2003) Dependences of drain current and conductance on drain bias

45 Schottky Barrier Height Engineering with Dopant Segregation (DS) Technique (VLSI’04, p.168)

46 Schottky Barrier Height Engineering with Dopant Segregation (DS) Technique (VLSI’04, p.168)

47 NiSi BF 2 + SDE Si FinFET with Modified-Schottky Barrier (MSB) IEEE Electron Device Lett., Vol. 25, p.430 (2004)

48 Source Drain Gate A A’ L g =25 nm Ni silicide Device Layout TEM Si FinFET with Modified-Schottky Barrier (MSB) IEEE Electron Device Lett., Vol. 25, p.430 (2004)

49 Si FinFET with Modified-Schottky Barrier (MSB) IEEE Electron Device Lett., Vol. 25, p.430 (2004)

50 Micro-structure of S/D in MSB FinFETs IEEE Electron Device Lett., Vol. 26, p.394 (2005) Fin width = 40 nm Fin width = 200 nm

51 Outline Background Low  B Source Field-induced Drain (FID) Structure Non-Si Channel Materials Interface Modulation Techniques Summary

52 Summary SB MOS devices may find applications in TFT and nano-CMOS manufacturing. A novel SB MOSFET with FID demonstrated. Based on the structure and unique ambipolar feature, a greatly simplified FEC characterization procedure developed for extracting the DOS in TFT. Nano-scale SOI device with excellent ambipolar subthrehsold swing and high on/off current ratio achieved.

53 Near-zero or even negative barrier height at source junction highly desired for practical SB MOSFET application. UTB SOI essential for leakage reduction Interface modulation processes are potential for future nano-scale device manufacturing. Summary (Cont.)